forked from tonioni/WinUAE
-
Notifications
You must be signed in to change notification settings - Fork 0
/
custom.cpp
16979 lines (15354 loc) · 433 KB
/
custom.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* UAE - The Un*x Amiga Emulator
*
* Custom chip emulation
*
* Copyright 1995-2002 Bernd Schmidt
* Copyright 1995 Alessandro Bissacco
* Copyright 2000-2023 Toni Wilen
*/
#include "sysconfig.h"
#include "sysdeps.h"
#include <ctype.h>
#include <assert.h>
#include <math.h>
#include "options.h"
#include "uae.h"
#include "gensound.h"
#include "audio.h"
#include "sounddep/sound.h"
#include "events.h"
#include "memory.h"
#include "custom.h"
#include "newcpu.h"
#include "cia.h"
#include "disk.h"
#include "blitter.h"
#include "xwin.h"
#include "inputdevice.h"
#ifdef SERIAL_PORT
#include "serial.h"
#endif
#include "autoconf.h"
#include "traps.h"
#include "gui.h"
#include "picasso96.h"
#include "drawing.h"
#include "savestate.h"
#include "ar.h"
#include "debug.h"
#include "akiko.h"
#if defined(ENFORCER)
#include "enforcer.h"
#endif
#include "threaddep/thread.h"
#include "luascript.h"
#include "devices.h"
#include "rommgr.h"
#include "specialmonitors.h"
#define BPL_ERASE_TEST 0
#define FRAMEWAIT_MIN_MS 2
#define FRAMEWAIT_SPLIT 4
#define CYCLE_CONFLICT_LOGGING 0
#define SPEEDUP 1
#define CUSTOM_DEBUG 0
#define SPRITE_DEBUG 0
#define SPRITE_DEBUG_MINY 0
#define SPRITE_DEBUG_MAXY 0x30
#define MAX_SPRITES 8
#define AUTOSCALE_SPRITES 1
#define ALL_SUBPIXEL 1
#define RGA_COPPER_PIPELINE_DEPTH 2
#define RGA_SPRITE_PIPELINE_DEPTH 2
#define REFRESH_FIRST_HPOS 3
#define DMAL_FIRST_HPOS 11
#define SPR_FIRST_HPOS 25
#define COPPER_CYCLE_POLARITY 0
#define HARDWIRED_DMA_TRIGGER_HPOS 1
#define REF_RAS_ADD_AGA 0x000
#define REF_RAS_ADD_ECS 0x200
#define REF_RAS_ADD_OCS 0x002
#define SPRBORDER 0
#define EXTRAWIDTH_BROADCAST 15
#define EXTRAHEIGHT_BROADCAST_TOP 0
#define EXTRAHEIGHT_BROADCAST_BOTTOM 0
#define EXTRAWIDTH_EXTREME 33
#define EXTRAHEIGHT_EXTREME 24
#define EXTRAWIDTH_ULTRA 77
#define LORES_TO_SHRES_SHIFT 2
#ifdef SERIAL_PORT
extern uae_u16 serper;
#endif
static void uae_abort (const TCHAR *format,...)
{
static int nomore;
va_list parms;
TCHAR buffer[1000];
va_start (parms, format);
_vsntprintf (buffer, sizeof (buffer) / sizeof(TCHAR) - 1, format, parms );
va_end (parms);
if (nomore) {
write_log (_T("%s\n"), buffer);
return;
}
gui_message (buffer);
nomore = 1;
}
static uae_u32 total_skipped = 0;
extern int cpu_last_stop_vpos, cpu_stopped_lines;
static int cpu_sleepmode, cpu_sleepmode_cnt;
extern int vsync_activeheight, vsync_totalheight;
extern float vsync_vblank, vsync_hblank;
/* Events */
evt_t vsync_cycles;
static int extra_cycle;
static int rpt_did_reset;
struct ev eventtab[ev_max];
struct ev2 eventtab2[ev2_max];
int vpos, vpos_prev, vposh;
static int hpos_hsync_extra;
static int vpos_count, vpos_count_diff;
int lof_store; // real bit in custom registers
int lof_display; // what display device thinks
int scandoubled_line;
static bool lof_lastline, lof_prev_lastline;
static int lol, lol_prev;
static bool linetoggle;
static int next_lineno;
static int linear_vpos;
static enum nln_how nextline_how;
static int lof_changed = 0, lof_changing = 0, interlace_changed = 0;
static int lof_changed_previous_field;
static int vposw_change;
static bool lof_lace;
static bool prevlofs[3];
static bool bplcon0_interlace_seen;
static bool vsync_rendered, frame_rendered, frame_shown;
static frame_time_t vsynctimeperline;
static frame_time_t frameskiptime;
static bool genlockhtoggle;
static bool genlockvtoggle;
static bool graphicsbuffer_retry;
static int cia_hsync;
static bool toscr_scanline_complex_bplcon1, toscr_scanline_complex_bplcon1_off;
static int toscr_hend;
static int nosignal_cnt, nosignal_status;
static bool nosignal_trigger;
static int issyncstopped_count;
int display_reset;
static evt_t line_start_cycles;
static bool initial_frame;
static evt_t custom_color_write_cycle;
static int color_writes_num;
static bool line_equ_freerun;
#define LOF_TOGGLES_NEEDED 3
//#define NLACE_CNT_NEEDED 50
static int lof_togglecnt_lace, lof_togglecnt_nlace; //, nlace_cnt;
/* Stupid genlock-detection prevention hack.
* We should stop calling vsync_handler() and
* hstop_handler() completely but it is not
* worth the trouble..
*/
static int vpos_previous, hpos_previous;
static int vpos_lpen, hpos_lpen, hhpos_lpen, lightpen_triggered;
int lightpen_x[2], lightpen_y[2];
int lightpen_cx[2], lightpen_cy[2], lightpen_active, lightpen_enabled, lightpen_enabled2;
static uae_u32 sprtaba[256],sprtabb[256];
static uae_u32 sprite_ab_merge[256];
/* Tables for collision detection. */
static uae_u32 sprclx[16], clxmask[16];
/* T genlock bit in ECS Denise and AGA color registers */
static uae_u8 color_regs_genlock[256];
/*
* Hardware registers of all sorts.
*/
static uae_u16 cregs[256];
uae_u16 intena, intreq;
static uae_u16 intena2, intreq2;
uae_u16 dmacon;
uae_u16 adkcon; /* used by audio code */
uae_u16 last_custom_value;
static bool dmacon_bpl, vdiwstate_bpl;
static uae_u32 cop1lc, cop2lc, copcon;
/*
* Horizontal defaults
*
* 0x00 0 HCB
* 0x01 1 HC1 (HSTART)
* 0x09 9 VR1 (HBLANK start)
* 0x12 18 SHS (Horizontal sync start)
* 0x1a 26 VER1 PAL
* 0x1b 27 VER1 NTSC
* 0x23 35 RHS (Horizontal sync end)
* 0x73 115 VR2
* 0x84 132 CEN (HCENTER)
* 0x8c 140 VER2 PAL (CEN->VER2 = CSYNC qualising pulse 2)
* 0x8d 141 VER2 NTSC
* 0xe2 226 HC226 (short line, selected if LOL=1, NTSC only)
* 0xe3 227 HC227 (NTSC long line/PAL)
*
* SHS->VER1 = CSYNC equalising pulse 1
* CEN->VER2 = CSYNC equalising pulse 2
*
* HC1->SHS = Inactivate part of CSYNC Vsync+Hsync pulse 1
* VR2->CEN = Inactivate part of CSYNC Vsync+HSync pulse 2
*
*
* Vertical defaults
*
* PAL
*
* 0 SVB
* 2 VC2
* 3 VC3
* 5 VC5
* 7 VC7
* 8 VC8
* 25 RVB (Vertical blank end)
* 311 VC311 short field (Vertical blank start)
* 312 VC312 long field (Vertical blank start)
*
* Odd field:
*
* HSYNC SHS to RHS
* VSYNC VC2/CEN to VC5/SHS
* CSYNC HSYNC + if VSYNC active: SHS to VER1 and CEN to VER2
*
* Vertical blank = VC312 + HC1 to RVB + HC1
* Vertical equalization = SVB + VR1 to VC7 + VR2
*
* Even field:
*
* HSYNC SHS to RHS
* VSYNC VC3/SHS to VC5/CEN
* CSYNC HSYNC + if VSYNC active: SHS to VER1 and CEN to VER2
*
* Vertical blank = VC311 + HC1 to RVB + HC1
* Vertical equalization start = SVB + VR2 to VC8 + VR1
*
*
* NTSC
*
* 0 SVB
* 3 VC3
* 6 VC6
* 9 VC9
* 20 RVB (Vertical blank end)
* 261 VC261 short field (Vertical blank start)
* 262 VC262 long field (Vertical blank start)
*
* Odd field:
*
* HSYNC SHS to RHS
* VSYNC VC3/SHS to VC6/SHS
* CSYNC HSYNC + if VSYNC active: SHS to VER1 and CEN to VER2
*
* Vertical blank = VC262/HC1 to RVB/HC1
* Vertical equalization = SVB/VR1 to VC9/VR1
*
* Even field:
*
* HSYNC SHS to RHS
* VSYNC VC3/CEN to VC6/CEN
* CSYNC HSYNC + if VSYNC active: SHS to VER1 and CEN to VER2
*
* Vertical blank = VC261/HC1 to RVB/HC1
* Vertical equalization = SVB/VR2 to VC9/VR2
*
*/
/*
* Bitplane DMA enable logic OCS/ECS differences:
*
* OCS: DDFSTRT hard start limit flag is disabled when horizontal hard start position matches.
* It is enabled during active bitplane DMA's last cycle. (Ending due to either DDFSTOP or hardstop match).
* ECS: DDFTSTR/STOP hard limit work as documented.
* It is cleared when hard start matches and set when hard stop matches.
*
* OCS hard start limit bug: if line didn't have BPL DMA active, next line's BPL DMA can start earlier than start limit.
* (See music disk Ode to Ramon by Digital Force, bottom scroller "scanline affect" )
* This feature also prevents multiple DDFSTRT/STOP regions in same scanline. ECS/AGA does not have this limit.
*
* DDFSTRT match is ignored if DMACON BPLEN is not enabled. ECS/AGA allows it. Does not affect DDFSTOP.
* Switch DMACON BPLEN off, wait value to DDFSTRT that matches during current scanline,
* switch BPLEN on: if OCS, bitplane DMA won't start, ECS/AGA: bitplane DMA starts.
*
*/
int maxhpos = MAXHPOS_PAL;
int maxhpos_short = MAXHPOS_PAL;
int maxvpos = MAXVPOS_PAL;
int maxvpos_nom = MAXVPOS_PAL; // nominal value (same as maxvpos but "faked" maxvpos in fake 60hz modes)
int maxvpos_display = MAXVPOS_PAL; // value used for display size
int maxhpos_display = AMIGA_WIDTH_MAX;
int maxvsize_display = AMIGA_HEIGHT_MAX;
int maxvpos_display_vsync; // extra lines from top visible in bottom
static bool maxvpos_display_vsync_next;
static int vblank_extraline;
static int maxhposm1;
int maxhposm0 = MAXHPOS_PAL;
static bool maxhposeven, maxhposeven_prev;
static int hsyncendpos, hsyncstartpos;
int hsync_end_left_border;
static int hsyncstartpos_start, hsyncstartpos_start_cycles;
static int hsyncstartpos_start_hw;
int hsyncstartpos_hw;
int hsyncendpos_hw;
int denisehtotal;
static int maxvpos_total = 511;
int minfirstline = VBLANK_ENDLINE_PAL;
int minfirstline_linear = VBLANK_ENDLINE_PAL;
static int firstblankedline;
static int equ_vblank_endline = EQU_ENDLINE_PAL;
static bool equ_vblank_toggle = true;
float vblank_hz = VBLANK_HZ_PAL, fake_vblank_hz, vblank_hz_stored, vblank_hz_nom;
float hblank_hz;
static float vblank_hz_lof, vblank_hz_shf, vblank_hz_lace;
static int vblank_hz_mult, vblank_hz_state;
static struct chipset_refresh *stored_chipset_refresh;
int doublescan;
int programmedmode;
frame_time_t syncbase;
static int fmode_saved, fmode;
uae_u16 beamcon0, new_beamcon0;
uae_u16 bemcon0_hsync_mask, bemcon0_vsync_mask;
static uae_u16 beamcon0_saved;
static uae_u16 bplcon0_saved, bplcon1_saved, bplcon2_saved;
static uae_u16 bplcon3_saved, bplcon4_saved;
static int varsync_changed, varsync_maybe_changed[2];
static int varhblank_lines, varhblank_val[2];
static int exthblank_lines[2];
static uae_u16 vt_old, ht_old, hs_old, vs_old;
uae_u16 vtotal, htotal;
static int maxvpos_stored, maxhpos_stored;
uae_u16 hsstop, hsstrt;
uae_u16 hbstop, hbstrt;
static int hsstop_detect, hsstop_detect2;
static uae_u16 vsstop, vsstrt;
static uae_u16 vbstop, vbstrt;
static uae_u16 hcenter, hcenter_v2, hcenter_v2_end, hcenter_sync_v2;
static bool hcenter_active;
static uae_u16 hbstop_v, hbstrt_v, hbstop_v2, hbstrt_v2, hbstop_sync_v2, hbstrt_sync_v2, hbstop_reg, hbstrt_reg;
static uae_u16 hsstrt_v2, hsstop_v2;
static int vsstrt_m, vsstop_m, vbstrt_m, vbstop_m;
static bool vb_state, vb_end_line;
static bool vs_state_var, vs_state_on, vs_state_on_old, vs_state_hw, vs_state_var_old;
static bool vb_end_next_line, vb_end_next_line2;
static int vb_start_line;
static bool ocs_blanked;
static uae_u16 sprhstrt, sprhstop, bplhstrt, bplhstop, hhpos, hhpos_hpos;
static uae_u16 sprhstrt_v, sprhstop_v, bplhstrt_v, bplhstop_v;
static int hhbpl, hhspr;
static int ciavsyncmode;
static int diw_hstrt, diw_hstop;
static int hdiw_counter;
static int hstrobe_hdiw_min;
static uae_u32 ref_ras_add;
static uaecptr refptr, refptr_p;
static uae_u32 refmask;
static int refresh_handled_slot;
static bool refptr_preupdated;
static bool hstrobe_conflict;
static uae_u16 strobe_vblank;
static bool vhposw_modified;
static int line_disabled;
static bool custom_disabled;
#define HSYNCTIME (maxhpos * CYCLE_UNIT)
struct sprite {
uaecptr pt;
int xpos;
int vstart;
int vstop;
int dblscan; /* AGA SSCAN2 */
int armed;
int dmastate;
int dmacycle;
int width;
bool ecs_denise_hires;
bool firstslotdone;
uae_u16 ctl, pos;
#ifdef AGA
uae_u16 data[4], datb[4];
#else
uae_u16 data[1], datb[1];
#endif
};
static struct sprite spr[MAX_SPRITES];
static int plfstrt_sprite;
static int sprbplconflict, sprbplconflict_hpos;
static int sprbplconflict2, sprbplconflict_hpos2;
static uae_u16 sprbplconflict_dat;
uaecptr sprite_0;
int sprite_0_width, sprite_0_height, sprite_0_doubled;
uae_u32 sprite_0_colors[4];
static uae_u8 magic_sprite_mask = 0xff;
static int hardwired_vbstrt, hardwired_vbstop;
static int last_sprite_point, last_sprite_point_abs;
static int nr_armed;
static int sprite_width, sprres;
static int sprite_sprctlmask;
int sprite_buffer_res;
uae_u8 cycle_line_slot[MAX_CHIPSETSLOTS + RGA_PIPELINE_ADJUST + MAX_CHIPSETSLOTS_EXTRA];
uae_u16 cycle_line_pipe[MAX_CHIPSETSLOTS + RGA_PIPELINE_ADJUST + MAX_CHIPSETSLOTS_EXTRA];
static uae_u8 cycle_line_slot_last;
static uae_s16 bpl1mod, bpl2mod, bpl1mod_prev, bpl2mod_prev;
static int bpl1mod_hpos, bpl2mod_hpos;
static uaecptr prevbpl[2][MAXVPOS][MAX_PLANES];
static uaecptr bplpt[MAX_PLANES], bplptx[MAX_PLANES];
static struct color_entry current_colors;
uae_u16 bplcon0;
static uae_u16 bplcon1, bplcon2, bplcon3, bplcon4;
static int bplcon0d, bplcon0d_old;
static bool bplcon0d_change;
static uae_u32 bplcon0_res, bplcon0_planes, bplcon0_planes_limit;
static int diwstrt, diwstop, diwhigh;
static int diwhigh_written;
static int ddfstrt, ddfstop, plfstop_prev;
static int ddfstrt_hpos, ddfstop_hpos;
static int line_cyclebased, diw_change;
static int bpl_shifter;
static void SET_LINE_CYCLEBASED(int hpos);
/* The display and data fetch windows */
enum class diw_states
{
DIW_waiting_start, DIW_waiting_stop
};
static int plffirstline, plflastline;
int plffirstline_total, plflastline_total;
int vblank_firstline_hw;
static int autoscale_bordercolors;
static int plfstrt, plfstop;
static int sprite_minx;
static int first_bpl_vpos;
static int last_decide_line_hpos;
static int last_fetch_hpos, last_decide_sprite_hpos;
static int diwfirstword, diwlastword;
static int last_diwlastword;
static int hb_last_diwlastword;
static int last_hdiw;
static diw_states vdiwstate, hdiwstate, hdiwstate_blank;
static int hdiwbplstart;
static int bpl_hstart;
static bool exthblank, exthblank_prev, exthblank_state, hcenterblank_state;
static int hsyncdebug;
static int last_diw_hpos;
static int last_recorded_diw_hpos;
static int last_hblank_start;
static int collision_hpos;
int first_planes_vpos, last_planes_vpos;
static int first_bplcon0, first_bplcon0_old;
static int first_planes_vpos_old, last_planes_vpos_old;
int diwfirstword_total, diwlastword_total;
int ddffirstword_total, ddflastword_total;
static int diwfirstword_total_old, diwlastword_total_old;
static int ddffirstword_total_old, ddflastword_total_old;
bool vertical_changed, horizontal_changed;
int firstword_bplcon1;
static int last_copper_hpos;
static int copper_access;
/* Sprite collisions */
static unsigned int clxdat, clxcon, clxcon2, clxcon_bpl_enable, clxcon_bpl_match;
enum copper_states {
COP_stop,
COP_waitforever,
COP_read1,
COP_read2,
COP_bltwait,
COP_bltwait2,
COP_wait_in2,
COP_skip_in2,
COP_wait1,
COP_wait,
COP_skip,
COP_skip1,
COP_strobe_delay1,
COP_strobe_delay2,
COP_strobe_delay3,
COP_strobe_delay4,
COP_strobe_delay5,
COP_strobe_delay1x,
COP_strobe_delay2x,
COP_strobe_extra, // just to skip current cycle when CPU wrote to COPJMP
COP_start_delay
};
struct copper {
/* The current instruction words. */
uae_u16 ir[2];
enum copper_states state, state_prev;
/* Instruction pointer. */
uaecptr ip;
// following move does not enable COPRS
int ignore_next;
int vcmp, hcmp;
int strobe; /* COPJMP1 / COPJMP2 accessed */
int last_strobe;
int moveaddr, movedata, movedelay;
uaecptr moveptr;
uaecptr vblankip;
};
static struct copper cop_state;
static int copper_enabled_thisline;
static evt_t copper_bad_cycle;
static uaecptr copper_bad_cycle_pc_old;
static evt_t copper_bad_cycle_start;
static uaecptr copper_bad_cycle_pc_new;
static evt_t copper_dma_change_cycle;
static evt_t blitter_dma_change_cycle;
static evt_t sprite_dma_change_cycle_on, sprite_dma_change_cycle_off;
/*
* Statistics
*/
uae_u32 timeframes;
evt_t frametime;
frame_time_t lastframetime;
uae_u32 hsync_counter, vsync_counter;
frame_time_t idletime;
int bogusframe;
static int display_vsync_counter;
/* Recording of custom chip register changes. */
static int current_change_set;
#define MAX_SPRITE_ENTRIES ((MAXVPOS + MAXVPOS_WRAPLINES) * 16)
static struct sprite_entry sprite_entries[2][MAX_SPRITE_ENTRIES];
static struct color_change color_changes[2][MAX_REG_CHANGE];
struct decision line_decisions[2 * (MAXVPOS + MAXVPOS_WRAPLINES) + 1];
static struct draw_info line_drawinfo[2][2 * (MAXVPOS + MAXVPOS_WRAPLINES) + 1];
#define COLOR_TABLE_SIZE (MAXVPOS + MAXVPOS_WRAPLINES) * 2
static struct color_entry color_tables[2][COLOR_TABLE_SIZE];
static int next_sprite_entry = 0, end_sprite_entry;
static int prev_next_sprite_entry;
static int next_sprite_forced = 1;
static int spixels_max;
struct sprite_entry *curr_sprite_entries, *prev_sprite_entries;
struct color_change *curr_color_changes, *prev_color_changes;
struct draw_info *curr_drawinfo, *prev_drawinfo;
struct color_entry *curr_color_tables, *prev_color_tables;
static int next_color_change, last_color_change;
static int next_color_entry, remembered_color_entry;
static int color_src_match, color_dest_match, color_compare_result;
static uae_u32 thisline_changed;
#ifdef SMART_UPDATE
#define MARK_LINE_CHANGED do { thisline_changed = 1; } while (0)
#else
#define MARK_LINE_CHANGED do { ; } while (0)
#endif
static struct decision thisline_decision;
static int fetch_cycle, fetch_modulo_cycle;
static bool ddf_limit, ddf_limit_latch, ddfstrt_match, hwi_old;
static int ddf_stopping, ddf_enable_on;
static int bprun, bprun_end;
static int bprun_cycle;
static int bprun_pipeline_flush_delay;
static bool plane0, plane0p, plane0p_enabled, plane0p_forced, plane0_first_done;
static int last_bpl1dat_hpos;
static bool last_bpl1dat_hpos_early;
static bool harddis_v, harddis_h;
static uae_u16 dmal_alloc_mask;
#define RGA_PIPELINE_OFFSET_BPL_WRITE 3
#define RGA_PIPELINE_OFFSET_COPPER 2
#define RGA_PIPELINE_OFFSET_SPRITE 2
#define RGA_PIPELINE_OFFSET_DMAL 2
struct custom_store custom_storage[256];
#define TOSCR_RES_PIXELS_LORES 4
#define TOSCR_RES_PIXELS_HIRES 2
#define TOSCR_RES_PIXELS_SHRES 1
#define TOSCR_NBITS 16
#define TOSCR_NBITSHR 32
static int out_nbits, out_offs;
static uae_u32 todisplay[MAX_PLANES], todisplay2[MAX_PLANES];
static uae_u32 outword[MAX_PLANES];
static uae_u64 outword64[MAX_PLANES], outword64_extra[MAX_PLANES];
static uae_u16 fetched[MAX_PLANES];
static uae_u16 todisplay_fetched;
#ifdef AGA
static uae_u64 todisplay_aga[MAX_PLANES], todisplay2_aga[MAX_PLANES];
static bool todisplay2_lastbit[MAX_PLANES];
static uae_u64 fetched_aga[MAX_PLANES];
static uae_u32 fetched_aga_spr[MAX_PLANES];
#endif
/* Expansions from bplcon0/bplcon1. */
static int toscr_res2p, toscr_res_mult;
static int toscr_res, toscr_res_old;
static int toscr_res_pixels, toscr_res_pixels_shift, toscr_res_pixels_shift_old;
static int toscr_res_pixels_hr, toscr_res_pixels_shift_hr, toscr_res_pixels_mask_hr, toscr_res_pixels_mask_hr_old, toscr_res_pixels_mask_hr2;
static int toscr_nr_planes, toscr_nr_planes2, toscr_nr_planes3, toscr_nr_planes_agnus;
static bool toscr_nr_changed;
static int toscr_nr_planes_shifter, toscr_nr_planes_shifter_new;
static int fetchwidth;
static int toscr_delay_adjusted[2], toscr_delay_sh[2];
static bool shdelay_disabled;
static int delay_cycles, delay_cycles2;
static int delay_lastcycle[2], delay_hsynccycle;
static int vhposr_delay_offset;
static bool bplcon1_written;
static bool bplcon0_planes_changed;
static bool sprites_enabled_this_line;
static int shifter_mask, toscr_delay_shifter[2];
static int out_subpix[2];
static bool speedup_first;
static void events_dmal(int);
static uae_u16 dmal, dmal_hpos;
static uae_u16 dmal_htotal_mask;
static bool dmal_ce;
static void update_copper(int until_hpos);
static void decide_sprites_fetch(int endhpos);
static void decide_line(int endhpos);
static void decide_sprites(int hpos, bool quick, bool halfcycle);
static void decide_sprites(int hpos);
/* The number of bits left from the last fetched words.
This is an optimization - conceptually, we have to make sure the result is
the same as if toscr is called in each clock cycle. However, to speed this
up, we accumulate display data; this variable keeps track of how much.
Thus, once we do call toscr_nbits (which happens at least every 16 bits),
we can do more work at once. */
static int toscr_nbits;
static int REGPARAM3 custom_wput_1(int, uaecptr, uae_u32, int) REGPARAM;
/*
* helper functions
*/
static bool safecpu(void)
{
return currprefs.cpu_model == 68000 && currprefs.cpu_cycle_exact && currprefs.blitter_cycle_exact && currprefs.m68k_speed == 0 && !(currprefs.cs_hacks & 16);
}
static void check_nocustom(void)
{
struct amigadisplay* ad = &adisplays[0];
if (ad->picasso_on && currprefs.picasso96_nocustom) {
custom_disabled = true;
line_disabled |= 2;
} else {
custom_disabled = false;
line_disabled &= ~2;
}
}
STATIC_INLINE bool ecsshres(void)
{
return bplcon0_res == RES_SUPERHIRES && ecs_denise && !aga_mode;
}
STATIC_INLINE bool nodraw(void)
{
struct amigadisplay *ad = &adisplays[0];
bool nd = !currprefs.cpu_memory_cycle_exact && ad->framecnt != 0;
return nd;
}
STATIC_INLINE int diw_to_hpos(int diw)
{
diw /= 4;
diw += DDF_OFFSET;
diw /= 2;
return diw;
}
STATIC_INLINE int hpos_to_diw(int pos)
{
return (pos * 2 - DDF_OFFSET) * 4;
}
STATIC_INLINE int hpos_to_diwx(int pos)
{
return ((pos + hpos_hsync_extra) * 2 - DDF_OFFSET) * 4;
}
static bool doflickerfix_possible(void)
{
return currprefs.gfx_vresolution && doublescan < 0 && vpos < MAXVPOS;
}
static bool doflickerfix_active(void)
{
return interlace_seen > 0 && doflickerfix_possible();
}
uae_u32 get_copper_address(int copno)
{
switch (copno) {
case 1: return cop1lc;
case 2: return cop2lc;
case 3: return cop_state.vblankip;
case -1: return cop_state.ip;
default: return 0;
}
}
void reset_frame_rate_hack(void)
{
if (currprefs.m68k_speed >= 0) {
return;
}
rpt_did_reset = 1;
events_reset_syncline();
vsyncmintime = read_processor_time() + vsynctimebase;
write_log(_T("Resetting frame rate hack\n"));
}
static void setclr(uae_u16 *p, uae_u16 val)
{
if (val & 0x8000) {
*p |= val & 0x7FFF;
} else {
*p &= ~val;
}
}
static int adjust_hr(int v)
{
if (currprefs.gfx_resolution >= RES_HIRES) {
if (currprefs.chipset_hr) {
v &= ~(3 >> currprefs.gfx_resolution);
} else {
v &= ~3;
}
} else {
v &= ~1;
}
return v;
}
static int adjust_hr2(int v)
{
if (currprefs.gfx_resolution >= RES_HIRES) {
if (currprefs.chipset_hr) {
v &= ~(1 >> currprefs.gfx_resolution);
} else {
v &= ~1;
}
}
return v;
}
STATIC_INLINE bool is_last_line(void)
{
return vpos + 1 == maxvpos + lof_store;
}
static void alloc_cycle(int hpos, int type)
{
#ifdef CPUEMU_13
#if CYCLE_CONFLICT_LOGGING
if (cycle_line_slot[hpos] && cycle_line_slot[hpos] != type) {
write_log(_T("alloc cycle conflict %d: %02x <- %02x\n"), hpos, type, cycle_line_slot[hpos]);
}
#endif
cycle_line_slot[hpos] = type;
#endif
}
static void alloc_cycle_maybe(int hpos, int type)
{
if ((cycle_line_slot[hpos] & CYCLE_MASK) == 0) {
alloc_cycle(hpos, type);
}
}
void alloc_cycle_ext(int hpos, int type)
{
alloc_cycle(hpos, type);
}
uaecptr alloc_cycle_blitter_conflict_or(int hpos, int chnum, bool *skip)
{
uaecptr orptr = 0;
if (copper_bad_cycle && line_start_cycles + hpos * CYCLE_UNIT == copper_bad_cycle) {
orptr = copper_bad_cycle_pc_old;
} else if (hpos == sprbplconflict_hpos2) {
uae_u16 bltdat = chnum == 4 ? 0x000 : (3 - chnum) * 2 + 0x70;
uae_u16 rga = bltdat & sprbplconflict2;
int spnum = (sprbplconflict2 - 0x140) / 8;
orptr = spr[spnum].pt;
if (rga != bltdat) {
*skip = true;
}
}
return orptr;
}
bool alloc_cycle_blitter(int hpos, uaecptr *ptr, int chnum, int add)
{
bool skipadd = false;
if (copper_bad_cycle && line_start_cycles + hpos * CYCLE_UNIT == copper_bad_cycle) {
write_log("Copper PT=%08x/%08x. Blitter CH=%d MOD=%d PT=%08x. Conflict bug!\n", copper_bad_cycle_pc_old, copper_bad_cycle_pc_new, chnum, add, *ptr);
cop_state.ip += add;
*ptr = copper_bad_cycle_pc_old;
skipadd = true;
copper_bad_cycle = 0;
} else if (hpos == sprbplconflict_hpos2) {
uae_u16 v = chipmem_wget_indirect(*ptr);
uae_u16 bltdat = chnum == 4 ? 0x000 : (3 - chnum) * 2 + 0x70;
uae_u16 rga = bltdat & sprbplconflict2;
int spnum = (sprbplconflict2 - 0x140) / 8;
uaecptr pt = spr[spnum].pt;
spr[spnum].pt = *ptr + 2 + add;
custom_wput_1(hpos, rga, v, 1);
sprbplconflict_hpos2 = -1;
#ifdef DEBUGGER
if (debug_dma) {
record_dma_read_value(v);
record_dma_read(rga, *ptr, hpos, vpos, DMARECORD_SPRITE, spnum);
}
#endif
write_log("Sprite %d. Blitter CH=%d MOD=%d PT=%08x. Conflict bug!\n", spnum, chnum, add, *ptr);
}
alloc_cycle(hpos, CYCLE_BLITTER);
return skipadd;
}
static int expand_sprres(uae_u16 con0, uae_u16 con3)
{
int res;
switch ((con3 >> 6) & 3)
{
default:
res = RES_LORES;
break;
#ifdef ECS_DENISE
case 0: /* ECS defaults (LORES,HIRES=LORES sprite,SHRES=HIRES sprite) */
if (ecs_denise && GET_RES_DENISE(con0) == RES_SUPERHIRES)
res = RES_HIRES;
else
res = RES_LORES;
break;
#endif
#ifdef AGA
case 1:
res = RES_LORES;
break;
case 2:
res = RES_HIRES;
break;
case 3:
res = RES_SUPERHIRES;
break;
#endif
}
return res;
}
static int islinetoggle(void)
{
int linetoggle = 0;
if (!(new_beamcon0 & BEAMCON0_LOLDIS) && !(new_beamcon0 & BEAMCON0_PAL) && ecs_agnus) {
linetoggle = 1; // NTSC and !LOLDIS -> LOL toggles every line
} else if (!ecs_agnus && currprefs.ntscmode) {
linetoggle = 1; // hardwired NTSC Agnus
}
return linetoggle;
}
STATIC_INLINE uae_u8 *pfield_xlateptr(uaecptr plpt, int bytecount)
{
if (!chipmem_check_indirect(plpt, bytecount)) {
static int count = 0;
if (!count) {
count++;
write_log(_T("Warning: Bad playfield pointer %08x\n"), plpt);
}
return NULL;
}
return chipmem_xlate_indirect(plpt);
}
static void docols(struct color_entry *colentry)
{
#ifdef AGA
if (aga_mode) {
for (int i = 0; i < 256; i++) {
int v = color_reg_get(colentry, i);
colentry->acolors[i] = getxcolor(v);
}
} else {
#endif
for (int i = 0; i < 32; i++) {
int v = color_reg_get(colentry, i);
colentry->acolors[i] = getxcolor(v);
}
#ifdef AGA
}
#endif
}
static void remember_ctable(void)
{
/* This can happen when program crashes very badly */
if (next_color_entry >= COLOR_TABLE_SIZE) {
return;
}
if (remembered_color_entry < 0) {
/* The colors changed since we last recorded a color map. Record a
* new one. */
color_reg_cpy(curr_color_tables + next_color_entry, ¤t_colors);
remembered_color_entry = next_color_entry++;
}
thisline_decision.ctable = remembered_color_entry;
if (color_src_match < 0 || color_dest_match != remembered_color_entry
|| line_decisions[next_lineno].ctable != color_src_match)
{
/* The remembered comparison didn't help us - need to compare again. */
int oldctable = line_decisions[next_lineno].ctable;
int changed = 0;
if (oldctable < 0) {
changed = 1;
color_src_match = color_dest_match = -1;
} else {
color_compare_result = color_reg_cmp(&prev_color_tables[oldctable], ¤t_colors) != 0;
if (color_compare_result) {
changed = 1;
}
color_src_match = oldctable;
color_dest_match = remembered_color_entry;
}
thisline_changed |= changed;
} else {
/* We know the result of the comparison */
if (color_compare_result) {
thisline_changed = 1;
}
}
}
static void remember_ctable_for_border(void)
{
remember_ctable();
}
static int get_equ_vblank_endline(void)
{
if (new_beamcon0 & (BEAMCON0_BLANKEN | BEAMCON0_VARCSYEN)) {
return -1;
}
return equ_vblank_endline + (equ_vblank_toggle ? (lof_store ? 1 : 0) : 0) + (agnusa1000 ? 1 : 0);
}