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Showing results

Pico Host Boot Loader

Rust 103 7 Updated Nov 4, 2024

GNU toolchain for RISC-V, including GCC

C 3,605 1,181 Updated Dec 11, 2024

Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from https://github.com/shioyadan/Konata/releases

JavaScript 406 38 Updated Apr 8, 2024

cv-jwhur

TeX 1 Updated Dec 5, 2024

Python module containing verilog files for marocchino cpu (for use with LiteX).

Verilog 1 Updated Sep 27, 2024

Linux kernel source tree

C 4 Updated Jul 21, 2021

VCD file (Value Change Dump) command line viewer

C 112 12 Updated Dec 17, 2022

The main Embench repository

C 260 104 Updated Aug 29, 2024

VPI library to load ELF files from verilog test benches

C 8 2 Updated Feb 11, 2021

Single-file makefile include that allows defining C/C++ makefiles with simple variable assignments.

Makefile 9 2 Updated Nov 2, 2024

The OpenRISC 1000 architectural simulator

C 72 43 Updated Aug 26, 2024

picolibc - a C library designed for embedded 32- and 64- bit systems.

C 1,185 182 Updated Dec 10, 2024

Yosys Open SYnthesis Suite

C++ 3,536 893 Updated Dec 13, 2024

An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!

Python 215 79 Updated May 21, 2022

Build your hardware, easily!

C 3,061 574 Updated Dec 12, 2024

ECP5 breakout board in a feather physical format

HTML 491 60 Updated Nov 6, 2024

mor1kx - an OpenRISC 1000 processor IP core

Verilog 503 147 Updated Oct 13, 2024

Open Processor Architecture

VHDL 26 3 Updated Apr 7, 2016

Collection of scripts that help dealing with ChangeLogs

Python 2 2 Updated Nov 9, 2018

Imaging, analysis, and simulation software for radio interferometry

Python 5,291 496 Updated Nov 13, 2024

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

C 63 20 Updated Dec 1, 2022

Picocli is a modern framework for building powerful, user-friendly, GraalVM-enabled command line apps with ease. It supports colors, autocompletion, subcommands, and more. In 1 source file so apps …

Java 4,949 425 Updated Dec 9, 2024

A simple, basic, formally verified UART controller

Verilog 283 48 Updated Jan 29, 2024

GCC port rewrite for OpenRISC

12 5 Updated Mar 18, 2023
1 Updated Jul 15, 2020

How To Retarget the GNU Toolchain in 21 Patches

82 15 Updated Jan 8, 2015

Source for openrisc.io

HTML 13 9 Updated Jul 12, 2023

Universal Advanced JTAG Debug Interface

SystemVerilog 17 11 Updated May 10, 2024

RISC-V CPU Core

SystemVerilog 294 50 Updated Jun 8, 2024

linux initramfs, testing, openocd, and other random utils for openrisc

Shell 3 Updated Dec 10, 2024
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