Hardware RTL Sources

core

This folder contains the core VHDL files for the NEORV32 CPU and the NEORV32 Processor. When creating a new synthesis/simulation project make sure to add all *.vhd files from this folder to a new design library called neorv32. The processor's top entity is neorv32_top.vhd.

Important

The sub-folder core/mem contains different platform-agnostic VHDL architectures of the processor-internal instruction and data memories (IMEM & DMEM). Make sure to add only one of each modules to the project's HDL file list. However, these default files can also be replaced by optimized technology-specific memory modules.

processor_templates

Contains pre-configured SoC templates that instantiate the processor's top entity from core. These templates can be instantiated directly within a FPGA-specific board wrapper.

system_integration

NEORV32 Processor wrappers dedicated for complex system integration:

• LiteX SoC builder
• Vivado IP integrator providing AXI4-lite and AXI4-stream interfaces

test_setups

Minimal processor test setups (FPGA- and board-independent) for checking out NEORV32. See the folder's README for more information. Note that these test setups are used in the NEORV32 User Guide.