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pinctrl-tegra20.c
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/*
* Pinctrl data for the NVIDIA Tegra20 pinmux
*
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
*
* Derived from code:
* Copyright (C) 2010 Google, Inc.
* Copyright (C) 2010 NVIDIA Corporation
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-tegra.h"
/*
* Most pins affected by the pinmux can also be GPIOs. Define these first.
* These must match how the GPIO driver names/numbers its pins.
*/
#define _GPIO(offset) (offset)
#define TEGRA_PIN_VI_GP6_PA0 _GPIO(0)
#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
#define TEGRA_PIN_SDIO3_CLK_PA6 _GPIO(6)
#define TEGRA_PIN_SDIO3_CMD_PA7 _GPIO(7)
#define TEGRA_PIN_GMI_AD17_PB0 _GPIO(8)
#define TEGRA_PIN_GMI_AD18_PB1 _GPIO(9)
#define TEGRA_PIN_LCD_PWR0_PB2 _GPIO(10)
#define TEGRA_PIN_LCD_PCLK_PB3 _GPIO(11)
#define TEGRA_PIN_SDIO3_DAT3_PB4 _GPIO(12)
#define TEGRA_PIN_SDIO3_DAT2_PB5 _GPIO(13)
#define TEGRA_PIN_SDIO3_DAT1_PB6 _GPIO(14)
#define TEGRA_PIN_SDIO3_DAT0_PB7 _GPIO(15)
#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
#define TEGRA_PIN_LCD_PWR1_PC1 _GPIO(17)
#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
#define TEGRA_PIN_LCD_PWR2_PC6 _GPIO(22)
#define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
#define TEGRA_PIN_SDIO3_DAT5_PD0 _GPIO(24)
#define TEGRA_PIN_SDIO3_DAT4_PD1 _GPIO(25)
#define TEGRA_PIN_VI_GP5_PD2 _GPIO(26)
#define TEGRA_PIN_SDIO3_DAT6_PD3 _GPIO(27)
#define TEGRA_PIN_SDIO3_DAT7_PD4 _GPIO(28)
#define TEGRA_PIN_VI_D1_PD5 _GPIO(29)
#define TEGRA_PIN_VI_VSYNC_PD6 _GPIO(30)
#define TEGRA_PIN_VI_HSYNC_PD7 _GPIO(31)
#define TEGRA_PIN_LCD_D0_PE0 _GPIO(32)
#define TEGRA_PIN_LCD_D1_PE1 _GPIO(33)
#define TEGRA_PIN_LCD_D2_PE2 _GPIO(34)
#define TEGRA_PIN_LCD_D3_PE3 _GPIO(35)
#define TEGRA_PIN_LCD_D4_PE4 _GPIO(36)
#define TEGRA_PIN_LCD_D5_PE5 _GPIO(37)
#define TEGRA_PIN_LCD_D6_PE6 _GPIO(38)
#define TEGRA_PIN_LCD_D7_PE7 _GPIO(39)
#define TEGRA_PIN_LCD_D8_PF0 _GPIO(40)
#define TEGRA_PIN_LCD_D9_PF1 _GPIO(41)
#define TEGRA_PIN_LCD_D10_PF2 _GPIO(42)
#define TEGRA_PIN_LCD_D11_PF3 _GPIO(43)
#define TEGRA_PIN_LCD_D12_PF4 _GPIO(44)
#define TEGRA_PIN_LCD_D13_PF5 _GPIO(45)
#define TEGRA_PIN_LCD_D14_PF6 _GPIO(46)
#define TEGRA_PIN_LCD_D15_PF7 _GPIO(47)
#define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
#define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
#define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
#define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
#define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
#define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
#define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
#define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
#define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
#define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
#define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
#define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
#define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
#define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
#define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
#define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
#define TEGRA_PIN_GMI_HIOW_N_PI0 _GPIO(64)
#define TEGRA_PIN_GMI_HIOR_N_PI1 _GPIO(65)
#define TEGRA_PIN_GMI_CS5_N_PI2 _GPIO(66)
#define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
#define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
#define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
#define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
#define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
#define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
#define TEGRA_PIN_LCD_DE_PJ1 _GPIO(73)
#define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
#define TEGRA_PIN_LCD_HSYNC_PJ3 _GPIO(75)
#define TEGRA_PIN_LCD_VSYNC_PJ4 _GPIO(76)
#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
#define TEGRA_PIN_GMI_AD16_PJ7 _GPIO(79)
#define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
#define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
#define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
#define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
#define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
#define TEGRA_PIN_GMI_AD19_PK7 _GPIO(87)
#define TEGRA_PIN_VI_D2_PL0 _GPIO(88)
#define TEGRA_PIN_VI_D3_PL1 _GPIO(89)
#define TEGRA_PIN_VI_D4_PL2 _GPIO(90)
#define TEGRA_PIN_VI_D5_PL3 _GPIO(91)
#define TEGRA_PIN_VI_D6_PL4 _GPIO(92)
#define TEGRA_PIN_VI_D7_PL5 _GPIO(93)
#define TEGRA_PIN_VI_D8_PL6 _GPIO(94)
#define TEGRA_PIN_VI_D9_PL7 _GPIO(95)
#define TEGRA_PIN_LCD_D16_PM0 _GPIO(96)
#define TEGRA_PIN_LCD_D17_PM1 _GPIO(97)
#define TEGRA_PIN_LCD_D18_PM2 _GPIO(98)
#define TEGRA_PIN_LCD_D19_PM3 _GPIO(99)
#define TEGRA_PIN_LCD_D20_PM4 _GPIO(100)
#define TEGRA_PIN_LCD_D21_PM5 _GPIO(101)
#define TEGRA_PIN_LCD_D22_PM6 _GPIO(102)
#define TEGRA_PIN_LCD_D23_PM7 _GPIO(103)
#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
#define TEGRA_PIN_LCD_CS0_N_PN4 _GPIO(108)
#define TEGRA_PIN_LCD_SDOUT_PN5 _GPIO(109)
#define TEGRA_PIN_LCD_DC0_PN6 _GPIO(110)
#define TEGRA_PIN_HDMI_INT_N_PN7 _GPIO(111)
#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
#define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
#define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
#define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
#define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
#define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
#define TEGRA_PIN_VI_PCLK_PT0 _GPIO(152)
#define TEGRA_PIN_VI_MCLK_PT1 _GPIO(153)
#define TEGRA_PIN_VI_D10_PT2 _GPIO(154)
#define TEGRA_PIN_VI_D11_PT3 _GPIO(155)
#define TEGRA_PIN_VI_D0_PT4 _GPIO(156)
#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
#define TEGRA_PIN_GMI_DPD_PT7 _GPIO(159)
#define TEGRA_PIN_PU0 _GPIO(160)
#define TEGRA_PIN_PU1 _GPIO(161)
#define TEGRA_PIN_PU2 _GPIO(162)
#define TEGRA_PIN_PU3 _GPIO(163)
#define TEGRA_PIN_PU4 _GPIO(164)
#define TEGRA_PIN_PU5 _GPIO(165)
#define TEGRA_PIN_PU6 _GPIO(166)
#define TEGRA_PIN_JTAG_RTCK_PU7 _GPIO(167)
#define TEGRA_PIN_PV0 _GPIO(168)
#define TEGRA_PIN_PV1 _GPIO(169)
#define TEGRA_PIN_PV2 _GPIO(170)
#define TEGRA_PIN_PV3 _GPIO(171)
#define TEGRA_PIN_PV4 _GPIO(172)
#define TEGRA_PIN_PV5 _GPIO(173)
#define TEGRA_PIN_PV6 _GPIO(174)
#define TEGRA_PIN_LCD_DC1_PV7 _GPIO(175)
#define TEGRA_PIN_LCD_CS1_N_PW0 _GPIO(176)
#define TEGRA_PIN_LCD_M1_PW1 _GPIO(177)
#define TEGRA_PIN_SPI2_CS1_N_PW2 _GPIO(178)
#define TEGRA_PIN_SPI2_CS2_N_PW3 _GPIO(179)
#define TEGRA_PIN_DAP_MCLK1_PW4 _GPIO(180)
#define TEGRA_PIN_DAP_MCLK2_PW5 _GPIO(181)
#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
#define TEGRA_PIN_SPI2_MOSI_PX0 _GPIO(184)
#define TEGRA_PIN_SPI2_MISO_PX1 _GPIO(185)
#define TEGRA_PIN_SPI2_SCK_PX2 _GPIO(186)
#define TEGRA_PIN_SPI2_CS0_N_PX3 _GPIO(187)
#define TEGRA_PIN_SPI1_MOSI_PX4 _GPIO(188)
#define TEGRA_PIN_SPI1_SCK_PX5 _GPIO(189)
#define TEGRA_PIN_SPI1_CS0_N_PX6 _GPIO(190)
#define TEGRA_PIN_SPI1_MISO_PX7 _GPIO(191)
#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
#define TEGRA_PIN_SDIO1_DAT3_PY4 _GPIO(196)
#define TEGRA_PIN_SDIO1_DAT2_PY5 _GPIO(197)
#define TEGRA_PIN_SDIO1_DAT1_PY6 _GPIO(198)
#define TEGRA_PIN_SDIO1_DAT0_PY7 _GPIO(199)
#define TEGRA_PIN_SDIO1_CLK_PZ0 _GPIO(200)
#define TEGRA_PIN_SDIO1_CMD_PZ1 _GPIO(201)
#define TEGRA_PIN_LCD_SDIN_PZ2 _GPIO(202)
#define TEGRA_PIN_LCD_WR_N_PZ3 _GPIO(203)
#define TEGRA_PIN_LCD_SCK_PZ4 _GPIO(204)
#define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
#define TEGRA_PIN_GMI_AD20_PAA0 _GPIO(208)
#define TEGRA_PIN_GMI_AD21_PAA1 _GPIO(209)
#define TEGRA_PIN_GMI_AD22_PAA2 _GPIO(210)
#define TEGRA_PIN_GMI_AD23_PAA3 _GPIO(211)
#define TEGRA_PIN_GMI_AD24_PAA4 _GPIO(212)
#define TEGRA_PIN_GMI_AD25_PAA5 _GPIO(213)
#define TEGRA_PIN_GMI_AD26_PAA6 _GPIO(214)
#define TEGRA_PIN_GMI_AD27_PAA7 _GPIO(215)
#define TEGRA_PIN_LED_BLINK_PBB0 _GPIO(216)
#define TEGRA_PIN_VI_GP0_PBB1 _GPIO(217)
#define TEGRA_PIN_CAM_I2C_SCL_PBB2 _GPIO(218)
#define TEGRA_PIN_CAM_I2C_SDA_PBB3 _GPIO(219)
#define TEGRA_PIN_VI_GP3_PBB4 _GPIO(220)
#define TEGRA_PIN_VI_GP4_PBB5 _GPIO(221)
#define TEGRA_PIN_PBB6 _GPIO(222)
#define TEGRA_PIN_PBB7 _GPIO(223)
/* All non-GPIO pins follow */
#define NUM_GPIOS (TEGRA_PIN_PBB7 + 1)
#define _PIN(offset) (NUM_GPIOS + (offset))
#define TEGRA_PIN_CRT_HSYNC _PIN(30)
#define TEGRA_PIN_CRT_VSYNC _PIN(31)
#define TEGRA_PIN_DDC_SCL _PIN(32)
#define TEGRA_PIN_DDC_SDA _PIN(33)
#define TEGRA_PIN_OWC _PIN(34)
#define TEGRA_PIN_CORE_PWR_REQ _PIN(35)
#define TEGRA_PIN_CPU_PWR_REQ _PIN(36)
#define TEGRA_PIN_PWR_INT_N _PIN(37)
#define TEGRA_PIN_CLK_32_K_IN _PIN(38)
#define TEGRA_PIN_DDR_COMP_PD _PIN(39)
#define TEGRA_PIN_DDR_COMP_PU _PIN(40)
#define TEGRA_PIN_DDR_A0 _PIN(41)
#define TEGRA_PIN_DDR_A1 _PIN(42)
#define TEGRA_PIN_DDR_A2 _PIN(43)
#define TEGRA_PIN_DDR_A3 _PIN(44)
#define TEGRA_PIN_DDR_A4 _PIN(45)
#define TEGRA_PIN_DDR_A5 _PIN(46)
#define TEGRA_PIN_DDR_A6 _PIN(47)
#define TEGRA_PIN_DDR_A7 _PIN(48)
#define TEGRA_PIN_DDR_A8 _PIN(49)
#define TEGRA_PIN_DDR_A9 _PIN(50)
#define TEGRA_PIN_DDR_A10 _PIN(51)
#define TEGRA_PIN_DDR_A11 _PIN(52)
#define TEGRA_PIN_DDR_A12 _PIN(53)
#define TEGRA_PIN_DDR_A13 _PIN(54)
#define TEGRA_PIN_DDR_A14 _PIN(55)
#define TEGRA_PIN_DDR_CAS_N _PIN(56)
#define TEGRA_PIN_DDR_BA0 _PIN(57)
#define TEGRA_PIN_DDR_BA1 _PIN(58)
#define TEGRA_PIN_DDR_BA2 _PIN(59)
#define TEGRA_PIN_DDR_DQS0P _PIN(60)
#define TEGRA_PIN_DDR_DQS0N _PIN(61)
#define TEGRA_PIN_DDR_DQS1P _PIN(62)
#define TEGRA_PIN_DDR_DQS1N _PIN(63)
#define TEGRA_PIN_DDR_DQS2P _PIN(64)
#define TEGRA_PIN_DDR_DQS2N _PIN(65)
#define TEGRA_PIN_DDR_DQS3P _PIN(66)
#define TEGRA_PIN_DDR_DQS3N _PIN(67)
#define TEGRA_PIN_DDR_CKE0 _PIN(68)
#define TEGRA_PIN_DDR_CKE1 _PIN(69)
#define TEGRA_PIN_DDR_CLK _PIN(70)
#define TEGRA_PIN_DDR_CLK_N _PIN(71)
#define TEGRA_PIN_DDR_DM0 _PIN(72)
#define TEGRA_PIN_DDR_DM1 _PIN(73)
#define TEGRA_PIN_DDR_DM2 _PIN(74)
#define TEGRA_PIN_DDR_DM3 _PIN(75)
#define TEGRA_PIN_DDR_ODT _PIN(76)
#define TEGRA_PIN_DDR_QUSE0 _PIN(77)
#define TEGRA_PIN_DDR_QUSE1 _PIN(78)
#define TEGRA_PIN_DDR_QUSE2 _PIN(79)
#define TEGRA_PIN_DDR_QUSE3 _PIN(80)
#define TEGRA_PIN_DDR_RAS_N _PIN(81)
#define TEGRA_PIN_DDR_WE_N _PIN(82)
#define TEGRA_PIN_DDR_DQ0 _PIN(83)
#define TEGRA_PIN_DDR_DQ1 _PIN(84)
#define TEGRA_PIN_DDR_DQ2 _PIN(85)
#define TEGRA_PIN_DDR_DQ3 _PIN(86)
#define TEGRA_PIN_DDR_DQ4 _PIN(87)
#define TEGRA_PIN_DDR_DQ5 _PIN(88)
#define TEGRA_PIN_DDR_DQ6 _PIN(89)
#define TEGRA_PIN_DDR_DQ7 _PIN(90)
#define TEGRA_PIN_DDR_DQ8 _PIN(91)
#define TEGRA_PIN_DDR_DQ9 _PIN(92)
#define TEGRA_PIN_DDR_DQ10 _PIN(93)
#define TEGRA_PIN_DDR_DQ11 _PIN(94)
#define TEGRA_PIN_DDR_DQ12 _PIN(95)
#define TEGRA_PIN_DDR_DQ13 _PIN(96)
#define TEGRA_PIN_DDR_DQ14 _PIN(97)
#define TEGRA_PIN_DDR_DQ15 _PIN(98)
#define TEGRA_PIN_DDR_DQ16 _PIN(99)
#define TEGRA_PIN_DDR_DQ17 _PIN(100)
#define TEGRA_PIN_DDR_DQ18 _PIN(101)
#define TEGRA_PIN_DDR_DQ19 _PIN(102)
#define TEGRA_PIN_DDR_DQ20 _PIN(103)
#define TEGRA_PIN_DDR_DQ21 _PIN(104)
#define TEGRA_PIN_DDR_DQ22 _PIN(105)
#define TEGRA_PIN_DDR_DQ23 _PIN(106)
#define TEGRA_PIN_DDR_DQ24 _PIN(107)
#define TEGRA_PIN_DDR_DQ25 _PIN(108)
#define TEGRA_PIN_DDR_DQ26 _PIN(109)
#define TEGRA_PIN_DDR_DQ27 _PIN(110)
#define TEGRA_PIN_DDR_DQ28 _PIN(111)
#define TEGRA_PIN_DDR_DQ29 _PIN(112)
#define TEGRA_PIN_DDR_DQ30 _PIN(113)
#define TEGRA_PIN_DDR_DQ31 _PIN(114)
#define TEGRA_PIN_DDR_CS0_N _PIN(115)
#define TEGRA_PIN_DDR_CS1_N _PIN(116)
#define TEGRA_PIN_SYS_RESET _PIN(117)
#define TEGRA_PIN_JTAG_TRST_N _PIN(118)
#define TEGRA_PIN_JTAG_TDO _PIN(119)
#define TEGRA_PIN_JTAG_TMS _PIN(120)
#define TEGRA_PIN_JTAG_TCK _PIN(121)
#define TEGRA_PIN_JTAG_TDI _PIN(122)
#define TEGRA_PIN_TEST_MODE_EN _PIN(123)
static const struct pinctrl_pin_desc tegra20_pins[] = {
PINCTRL_PIN(TEGRA_PIN_VI_GP6_PA0, "VI_GP6 PA0"),
PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_CLK_PA6, "SDIO3_CLK PA6"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_CMD_PA7, "SDIO3_CMD PA7"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD17_PB0, "GMI_AD17 PB0"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD18_PB1, "GMI_AD18 PB1"),
PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT3_PB4, "SDIO3_DAT3 PB4"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT2_PB5, "SDIO3_DAT2 PB5"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT1_PB6, "SDIO3_DAT1 PB6"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT0_PB7, "SDIO3_DAT0 PB7"),
PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT5_PD0, "SDIO3_DAT5 PD0"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT4_PD1, "SDIO3_DAT4 PD1"),
PINCTRL_PIN(TEGRA_PIN_VI_GP5_PD2, "VI_GP5 PD2"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT6_PD3, "SDIO3_DAT6 PD3"),
PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT7_PD4, "SDIO3_DAT7 PD4"),
PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
PINCTRL_PIN(TEGRA_PIN_LCD_D0_PE0, "LCD_D0 PE0"),
PINCTRL_PIN(TEGRA_PIN_LCD_D1_PE1, "LCD_D1 PE1"),
PINCTRL_PIN(TEGRA_PIN_LCD_D2_PE2, "LCD_D2 PE2"),
PINCTRL_PIN(TEGRA_PIN_LCD_D3_PE3, "LCD_D3 PE3"),
PINCTRL_PIN(TEGRA_PIN_LCD_D4_PE4, "LCD_D4 PE4"),
PINCTRL_PIN(TEGRA_PIN_LCD_D5_PE5, "LCD_D5 PE5"),
PINCTRL_PIN(TEGRA_PIN_LCD_D6_PE6, "LCD_D6 PE6"),
PINCTRL_PIN(TEGRA_PIN_LCD_D7_PE7, "LCD_D7 PE7"),
PINCTRL_PIN(TEGRA_PIN_LCD_D8_PF0, "LCD_D8 PF0"),
PINCTRL_PIN(TEGRA_PIN_LCD_D9_PF1, "LCD_D9 PF1"),
PINCTRL_PIN(TEGRA_PIN_LCD_D10_PF2, "LCD_D10 PF2"),
PINCTRL_PIN(TEGRA_PIN_LCD_D11_PF3, "LCD_D11 PF3"),
PINCTRL_PIN(TEGRA_PIN_LCD_D12_PF4, "LCD_D12 PF4"),
PINCTRL_PIN(TEGRA_PIN_LCD_D13_PF5, "LCD_D13 PF5"),
PINCTRL_PIN(TEGRA_PIN_LCD_D14_PF6, "LCD_D14 PF6"),
PINCTRL_PIN(TEGRA_PIN_LCD_D15_PF7, "LCD_D15 PF7"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
PINCTRL_PIN(TEGRA_PIN_GMI_HIOW_N_PI0, "GMI_HIOW_N PI0"),
PINCTRL_PIN(TEGRA_PIN_GMI_HIOR_N_PI1, "GMI_HIOR_N PI1"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS5_N_PI2, "GMI_CS5_N PI2"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
PINCTRL_PIN(TEGRA_PIN_LCD_DE_PJ1, "LCD_DE PJ1"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
PINCTRL_PIN(TEGRA_PIN_LCD_HSYNC_PJ3, "LCD_HSYNC PJ3"),
PINCTRL_PIN(TEGRA_PIN_LCD_VSYNC_PJ4, "LCD_VSYNC PJ4"),
PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD16_PJ7, "GMI_AD16 PJ7"),
PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD19_PK7, "GMI_AD19 PK7"),
PINCTRL_PIN(TEGRA_PIN_VI_D2_PL0, "VI_D2 PL0"),
PINCTRL_PIN(TEGRA_PIN_VI_D3_PL1, "VI_D3 PL1"),
PINCTRL_PIN(TEGRA_PIN_VI_D4_PL2, "VI_D4 PL2"),
PINCTRL_PIN(TEGRA_PIN_VI_D5_PL3, "VI_D5 PL3"),
PINCTRL_PIN(TEGRA_PIN_VI_D6_PL4, "VI_D6 PL4"),
PINCTRL_PIN(TEGRA_PIN_VI_D7_PL5, "VI_D7 PL5"),
PINCTRL_PIN(TEGRA_PIN_VI_D8_PL6, "VI_D8 PL6"),
PINCTRL_PIN(TEGRA_PIN_VI_D9_PL7, "VI_D9 PL7"),
PINCTRL_PIN(TEGRA_PIN_LCD_D16_PM0, "LCD_D16 PM0"),
PINCTRL_PIN(TEGRA_PIN_LCD_D17_PM1, "LCD_D17 PM1"),
PINCTRL_PIN(TEGRA_PIN_LCD_D18_PM2, "LCD_D18 PM2"),
PINCTRL_PIN(TEGRA_PIN_LCD_D19_PM3, "LCD_D19 PM3"),
PINCTRL_PIN(TEGRA_PIN_LCD_D20_PM4, "LCD_D20 PM4"),
PINCTRL_PIN(TEGRA_PIN_LCD_D21_PM5, "LCD_D21 PM5"),
PINCTRL_PIN(TEGRA_PIN_LCD_D22_PM6, "LCD_D22 PM6"),
PINCTRL_PIN(TEGRA_PIN_LCD_D23_PM7, "LCD_D23 PM7"),
PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
PINCTRL_PIN(TEGRA_PIN_LCD_CS0_N_PN4, "LCD_CS0_N PN4"),
PINCTRL_PIN(TEGRA_PIN_LCD_SDOUT_PN5, "LCD_SDOUT PN5"),
PINCTRL_PIN(TEGRA_PIN_LCD_DC0_PN6, "LCD_DC0 PN6"),
PINCTRL_PIN(TEGRA_PIN_HDMI_INT_N_PN7, "HDMI_INT_N PN7"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
PINCTRL_PIN(TEGRA_PIN_VI_PCLK_PT0, "VI_PCLK PT0"),
PINCTRL_PIN(TEGRA_PIN_VI_MCLK_PT1, "VI_MCLK PT1"),
PINCTRL_PIN(TEGRA_PIN_VI_D10_PT2, "VD_D10 PT2"),
PINCTRL_PIN(TEGRA_PIN_VI_D11_PT3, "VI_D11 PT3"),
PINCTRL_PIN(TEGRA_PIN_VI_D0_PT4, "VI_D0 PT4"),
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
PINCTRL_PIN(TEGRA_PIN_GMI_DPD_PT7, "GMI_DPD PT7"),
/* PU0..6: GPIO only */
PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK_PU7, "JTAG_RTCK PU7"),
/* PV0..1: GPIO only */
PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
/* PV2..3: Balls are named after GPIO not function */
PINCTRL_PIN(TEGRA_PIN_PV2, "PV2"),
PINCTRL_PIN(TEGRA_PIN_PV3, "PV3"),
/* PV4..6: GPIO only */
PINCTRL_PIN(TEGRA_PIN_PV4, "PV4"),
PINCTRL_PIN(TEGRA_PIN_PV5, "PV5"),
PINCTRL_PIN(TEGRA_PIN_PV6, "PV6"),
PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PV7, "LCD_DC1 PV7"),
PINCTRL_PIN(TEGRA_PIN_LCD_CS1_N_PW0, "LCD_CS1_N PW0"),
PINCTRL_PIN(TEGRA_PIN_LCD_M1_PW1, "LCD_M1 PW1"),
PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_N_PW2, "SPI2_CS1_N PW2"),
PINCTRL_PIN(TEGRA_PIN_SPI2_CS2_N_PW3, "SPI2_CS2_N PW3"),
PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
PINCTRL_PIN(TEGRA_PIN_DAP_MCLK2_PW5, "DAP_MCLK2 PW5"),
PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PX0, "SPI2_MOSI PX0"),
PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PX1, "SPI2_MISO PX1"),
PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PX2, "SPI2_SCK PX2"),
PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PX3, "SPI2_CS0_N PX3"),
PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PX4, "SPI1_MOSI PX4"),
PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PX5, "SPI1_SCK PX5"),
PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_N_PX6, "SPI1_CS0_N PX6"),
PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PX7, "SPI1_MISO PX7"),
PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT3_PY4, "SDIO1_DAT3 PY4"),
PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT2_PY5, "SDIO1_DAT2 PY5"),
PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT1_PY6, "SDIO1_DAT1 PY6"),
PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT0_PY7, "SDIO1_DAT0 PY7"),
PINCTRL_PIN(TEGRA_PIN_SDIO1_CLK_PZ0, "SDIO1_CLK PZ0"),
PINCTRL_PIN(TEGRA_PIN_SDIO1_CMD_PZ1, "SDIO1_CMD PZ1"),
PINCTRL_PIN(TEGRA_PIN_LCD_SDIN_PZ2, "LCD_SDIN PZ2"),
PINCTRL_PIN(TEGRA_PIN_LCD_WR_N_PZ3, "LCD_WR_N PZ3"),
PINCTRL_PIN(TEGRA_PIN_LCD_SCK_PZ4, "LCD_SCK PZ4"),
PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD20_PAA0, "GMI_AD20 PAA0"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD21_PAA1, "GMI_AD21 PAA1"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD22_PAA2, "GMI_AD22 PAA2"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD23_PAA3, "GMI_AD23 PAA3"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD24_PAA4, "GMI_AD24 PAA4"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD25_PAA5, "GMI_AD25 PAA5"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD26_PAA6, "GMI_AD26 PAA6"),
PINCTRL_PIN(TEGRA_PIN_GMI_AD27_PAA7, "GMI_AD27 PAA7"),
PINCTRL_PIN(TEGRA_PIN_LED_BLINK_PBB0, "LED_BLINK PBB0"),
PINCTRL_PIN(TEGRA_PIN_VI_GP0_PBB1, "VI_GP0 PBB1"),
PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB2, "CAM_I2C_SCL PBB2"),
PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB3, "CAM_I2C_SDA PBB3"),
PINCTRL_PIN(TEGRA_PIN_VI_GP3_PBB4, "VI_GP3 PBB4"),
PINCTRL_PIN(TEGRA_PIN_VI_GP4_PBB5, "VI_GP4 PBB5"),
PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
PINCTRL_PIN(TEGRA_PIN_CRT_HSYNC, "CRT_HSYNC"),
PINCTRL_PIN(TEGRA_PIN_CRT_VSYNC, "CRT_VSYNC"),
PINCTRL_PIN(TEGRA_PIN_DDC_SCL, "DDC_SCL"),
PINCTRL_PIN(TEGRA_PIN_DDC_SDA, "DDC_SDA"),
PINCTRL_PIN(TEGRA_PIN_OWC, "OWC"),
PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
PINCTRL_PIN(TEGRA_PIN_CLK_32_K_IN, "CLK_32_K_IN"),
PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PD, "DDR_COMP_PD"),
PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PU, "DDR_COMP_PU"),
PINCTRL_PIN(TEGRA_PIN_DDR_A0, "DDR_A0"),
PINCTRL_PIN(TEGRA_PIN_DDR_A1, "DDR_A1"),
PINCTRL_PIN(TEGRA_PIN_DDR_A2, "DDR_A2"),
PINCTRL_PIN(TEGRA_PIN_DDR_A3, "DDR_A3"),
PINCTRL_PIN(TEGRA_PIN_DDR_A4, "DDR_A4"),
PINCTRL_PIN(TEGRA_PIN_DDR_A5, "DDR_A5"),
PINCTRL_PIN(TEGRA_PIN_DDR_A6, "DDR_A6"),
PINCTRL_PIN(TEGRA_PIN_DDR_A7, "DDR_A7"),
PINCTRL_PIN(TEGRA_PIN_DDR_A8, "DDR_A8"),
PINCTRL_PIN(TEGRA_PIN_DDR_A9, "DDR_A9"),
PINCTRL_PIN(TEGRA_PIN_DDR_A10, "DDR_A10"),
PINCTRL_PIN(TEGRA_PIN_DDR_A11, "DDR_A11"),
PINCTRL_PIN(TEGRA_PIN_DDR_A12, "DDR_A12"),
PINCTRL_PIN(TEGRA_PIN_DDR_A13, "DDR_A13"),
PINCTRL_PIN(TEGRA_PIN_DDR_A14, "DDR_A14"),
PINCTRL_PIN(TEGRA_PIN_DDR_CAS_N, "DDR_CAS_N"),
PINCTRL_PIN(TEGRA_PIN_DDR_BA0, "DDR_BA0"),
PINCTRL_PIN(TEGRA_PIN_DDR_BA1, "DDR_BA1"),
PINCTRL_PIN(TEGRA_PIN_DDR_BA2, "DDR_BA2"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQS0P, "DDR_DQS0P"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQS0N, "DDR_DQS0N"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQS1P, "DDR_DQS1P"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQS1N, "DDR_DQS1N"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQS2P, "DDR_DQS2P"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQS2N, "DDR_DQS2N"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQS3P, "DDR_DQS3P"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQS3N, "DDR_DQS3N"),
PINCTRL_PIN(TEGRA_PIN_DDR_CKE0, "DDR_CKE0"),
PINCTRL_PIN(TEGRA_PIN_DDR_CKE1, "DDR_CKE1"),
PINCTRL_PIN(TEGRA_PIN_DDR_CLK, "DDR_CLK"),
PINCTRL_PIN(TEGRA_PIN_DDR_CLK_N, "DDR_CLK_N"),
PINCTRL_PIN(TEGRA_PIN_DDR_DM0, "DDR_DM0"),
PINCTRL_PIN(TEGRA_PIN_DDR_DM1, "DDR_DM1"),
PINCTRL_PIN(TEGRA_PIN_DDR_DM2, "DDR_DM2"),
PINCTRL_PIN(TEGRA_PIN_DDR_DM3, "DDR_DM3"),
PINCTRL_PIN(TEGRA_PIN_DDR_ODT, "DDR_ODT"),
PINCTRL_PIN(TEGRA_PIN_DDR_QUSE0, "DDR_QUSE0"),
PINCTRL_PIN(TEGRA_PIN_DDR_QUSE1, "DDR_QUSE1"),
PINCTRL_PIN(TEGRA_PIN_DDR_QUSE2, "DDR_QUSE2"),
PINCTRL_PIN(TEGRA_PIN_DDR_QUSE3, "DDR_QUSE3"),
PINCTRL_PIN(TEGRA_PIN_DDR_RAS_N, "DDR_RAS_N"),
PINCTRL_PIN(TEGRA_PIN_DDR_WE_N, "DDR_WE_N"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ0, "DDR_DQ0"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ1, "DDR_DQ1"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ2, "DDR_DQ2"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ3, "DDR_DQ3"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ4, "DDR_DQ4"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ5, "DDR_DQ5"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ6, "DDR_DQ6"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ7, "DDR_DQ7"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ8, "DDR_DQ8"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ9, "DDR_DQ9"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ10, "DDR_DQ10"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ11, "DDR_DQ11"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ12, "DDR_DQ12"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ13, "DDR_DQ13"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ14, "DDR_DQ14"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ15, "DDR_DQ15"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ16, "DDR_DQ16"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ17, "DDR_DQ17"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ18, "DDR_DQ18"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ19, "DDR_DQ19"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ20, "DDR_DQ20"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ21, "DDR_DQ21"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ22, "DDR_DQ22"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ23, "DDR_DQ23"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ24, "DDR_DQ24"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ25, "DDR_DQ25"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ26, "DDR_DQ26"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ27, "DDR_DQ27"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ28, "DDR_DQ28"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ29, "DDR_DQ29"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ30, "DDR_DQ30"),
PINCTRL_PIN(TEGRA_PIN_DDR_DQ31, "DDR_DQ31"),
PINCTRL_PIN(TEGRA_PIN_DDR_CS0_N, "DDR_CS0_N"),
PINCTRL_PIN(TEGRA_PIN_DDR_CS1_N, "DDR_CS1_N"),
PINCTRL_PIN(TEGRA_PIN_SYS_RESET, "SYS_RESET"),
PINCTRL_PIN(TEGRA_PIN_JTAG_TRST_N, "JTAG_TRST_N"),
PINCTRL_PIN(TEGRA_PIN_JTAG_TDO, "JTAG_TDO"),
PINCTRL_PIN(TEGRA_PIN_JTAG_TMS, "JTAG_TMS"),
PINCTRL_PIN(TEGRA_PIN_JTAG_TCK, "JTAG_TCK"),
PINCTRL_PIN(TEGRA_PIN_JTAG_TDI, "JTAG_TDI"),
PINCTRL_PIN(TEGRA_PIN_TEST_MODE_EN, "TEST_MODE_EN"),
};
static const unsigned ata_pins[] = {
TEGRA_PIN_GMI_CS6_N_PI3,
TEGRA_PIN_GMI_CS7_N_PI6,
TEGRA_PIN_GMI_RST_N_PI4,
};
static const unsigned atb_pins[] = {
TEGRA_PIN_GMI_CS5_N_PI2,
TEGRA_PIN_GMI_DPD_PT7,
};
static const unsigned atc_pins[] = {
TEGRA_PIN_GMI_IORDY_PI5,
TEGRA_PIN_GMI_WAIT_PI7,
TEGRA_PIN_GMI_ADV_N_PK0,
TEGRA_PIN_GMI_CLK_PK1,
TEGRA_PIN_GMI_CS2_N_PK3,
TEGRA_PIN_GMI_CS3_N_PK4,
TEGRA_PIN_GMI_CS4_N_PK2,
TEGRA_PIN_GMI_AD0_PG0,
TEGRA_PIN_GMI_AD1_PG1,
TEGRA_PIN_GMI_AD2_PG2,
TEGRA_PIN_GMI_AD3_PG3,
TEGRA_PIN_GMI_AD4_PG4,
TEGRA_PIN_GMI_AD5_PG5,
TEGRA_PIN_GMI_AD6_PG6,
TEGRA_PIN_GMI_AD7_PG7,
TEGRA_PIN_GMI_HIOW_N_PI0,
TEGRA_PIN_GMI_HIOR_N_PI1,
};
static const unsigned atd_pins[] = {
TEGRA_PIN_GMI_AD8_PH0,
TEGRA_PIN_GMI_AD9_PH1,
TEGRA_PIN_GMI_AD10_PH2,
TEGRA_PIN_GMI_AD11_PH3,
};
static const unsigned ate_pins[] = {
TEGRA_PIN_GMI_AD12_PH4,
TEGRA_PIN_GMI_AD13_PH5,
TEGRA_PIN_GMI_AD14_PH6,
TEGRA_PIN_GMI_AD15_PH7,
};
static const unsigned cdev1_pins[] = {
TEGRA_PIN_DAP_MCLK1_PW4,
};
static const unsigned cdev2_pins[] = {
TEGRA_PIN_DAP_MCLK2_PW5,
};
static const unsigned crtp_pins[] = {
TEGRA_PIN_CRT_HSYNC,
TEGRA_PIN_CRT_VSYNC,
};
static const unsigned csus_pins[] = {
TEGRA_PIN_VI_MCLK_PT1,
};
static const unsigned dap1_pins[] = {
TEGRA_PIN_DAP1_FS_PN0,
TEGRA_PIN_DAP1_DIN_PN1,
TEGRA_PIN_DAP1_DOUT_PN2,
TEGRA_PIN_DAP1_SCLK_PN3,
};
static const unsigned dap2_pins[] = {
TEGRA_PIN_DAP2_FS_PA2,
TEGRA_PIN_DAP2_SCLK_PA3,
TEGRA_PIN_DAP2_DIN_PA4,
TEGRA_PIN_DAP2_DOUT_PA5,
};
static const unsigned dap3_pins[] = {
TEGRA_PIN_DAP3_FS_PP0,
TEGRA_PIN_DAP3_DIN_PP1,
TEGRA_PIN_DAP3_DOUT_PP2,
TEGRA_PIN_DAP3_SCLK_PP3,
};
static const unsigned dap4_pins[] = {
TEGRA_PIN_DAP4_FS_PP4,
TEGRA_PIN_DAP4_DIN_PP5,
TEGRA_PIN_DAP4_DOUT_PP6,
TEGRA_PIN_DAP4_SCLK_PP7,
};
static const unsigned ddc_pins[] = {
TEGRA_PIN_DDC_SCL,
TEGRA_PIN_DDC_SDA,
};
static const unsigned dta_pins[] = {
TEGRA_PIN_VI_D0_PT4,
TEGRA_PIN_VI_D1_PD5,
};
static const unsigned dtb_pins[] = {
TEGRA_PIN_VI_D10_PT2,
TEGRA_PIN_VI_D11_PT3,
};
static const unsigned dtc_pins[] = {
TEGRA_PIN_VI_HSYNC_PD7,
TEGRA_PIN_VI_VSYNC_PD6,
};
static const unsigned dtd_pins[] = {
TEGRA_PIN_VI_PCLK_PT0,
TEGRA_PIN_VI_D2_PL0,
TEGRA_PIN_VI_D3_PL1,
TEGRA_PIN_VI_D4_PL2,
TEGRA_PIN_VI_D5_PL3,
TEGRA_PIN_VI_D6_PL4,
TEGRA_PIN_VI_D7_PL5,
TEGRA_PIN_VI_D8_PL6,
TEGRA_PIN_VI_D9_PL7,
};
static const unsigned dte_pins[] = {
TEGRA_PIN_VI_GP0_PBB1,
TEGRA_PIN_VI_GP3_PBB4,
TEGRA_PIN_VI_GP4_PBB5,
TEGRA_PIN_VI_GP5_PD2,
TEGRA_PIN_VI_GP6_PA0,
};
static const unsigned dtf_pins[] = {
TEGRA_PIN_CAM_I2C_SCL_PBB2,
TEGRA_PIN_CAM_I2C_SDA_PBB3,
};
static const unsigned gma_pins[] = {
TEGRA_PIN_GMI_AD20_PAA0,
TEGRA_PIN_GMI_AD21_PAA1,
TEGRA_PIN_GMI_AD22_PAA2,
TEGRA_PIN_GMI_AD23_PAA3,
};
static const unsigned gmb_pins[] = {
TEGRA_PIN_GMI_WP_N_PC7,
};
static const unsigned gmc_pins[] = {
TEGRA_PIN_GMI_AD16_PJ7,
TEGRA_PIN_GMI_AD17_PB0,
TEGRA_PIN_GMI_AD18_PB1,
TEGRA_PIN_GMI_AD19_PK7,
};
static const unsigned gmd_pins[] = {
TEGRA_PIN_GMI_CS0_N_PJ0,
TEGRA_PIN_GMI_CS1_N_PJ2,
};
static const unsigned gme_pins[] = {
TEGRA_PIN_GMI_AD24_PAA4,
TEGRA_PIN_GMI_AD25_PAA5,
TEGRA_PIN_GMI_AD26_PAA6,
TEGRA_PIN_GMI_AD27_PAA7,
};
static const unsigned gpu_pins[] = {
TEGRA_PIN_PU0,
TEGRA_PIN_PU1,
TEGRA_PIN_PU2,
TEGRA_PIN_PU3,
TEGRA_PIN_PU4,
TEGRA_PIN_PU5,
TEGRA_PIN_PU6,
};
static const unsigned gpu7_pins[] = {
TEGRA_PIN_JTAG_RTCK_PU7,
};
static const unsigned gpv_pins[] = {
TEGRA_PIN_PV4,
TEGRA_PIN_PV5,
TEGRA_PIN_PV6,
};
static const unsigned hdint_pins[] = {
TEGRA_PIN_HDMI_INT_N_PN7,
};
static const unsigned i2cp_pins[] = {
TEGRA_PIN_PWR_I2C_SCL_PZ6,
TEGRA_PIN_PWR_I2C_SDA_PZ7,
};
static const unsigned irrx_pins[] = {
TEGRA_PIN_UART2_RTS_N_PJ6,
};
static const unsigned irtx_pins[] = {
TEGRA_PIN_UART2_CTS_N_PJ5,
};
static const unsigned kbca_pins[] = {
TEGRA_PIN_KB_ROW0_PR0,
TEGRA_PIN_KB_ROW1_PR1,
TEGRA_PIN_KB_ROW2_PR2,
};
static const unsigned kbcb_pins[] = {
TEGRA_PIN_KB_ROW7_PR7,
TEGRA_PIN_KB_ROW8_PS0,
TEGRA_PIN_KB_ROW9_PS1,
TEGRA_PIN_KB_ROW10_PS2,
TEGRA_PIN_KB_ROW11_PS3,
TEGRA_PIN_KB_ROW12_PS4,
TEGRA_PIN_KB_ROW13_PS5,
TEGRA_PIN_KB_ROW14_PS6,
TEGRA_PIN_KB_ROW15_PS7,
};
static const unsigned kbcc_pins[] = {
TEGRA_PIN_KB_COL0_PQ0,
TEGRA_PIN_KB_COL1_PQ1,
};
static const unsigned kbcd_pins[] = {
TEGRA_PIN_KB_ROW3_PR3,
TEGRA_PIN_KB_ROW4_PR4,
TEGRA_PIN_KB_ROW5_PR5,
TEGRA_PIN_KB_ROW6_PR6,
};
static const unsigned kbce_pins[] = {
TEGRA_PIN_KB_COL7_PQ7,
};
static const unsigned kbcf_pins[] = {
TEGRA_PIN_KB_COL2_PQ2,
TEGRA_PIN_KB_COL3_PQ3,
TEGRA_PIN_KB_COL4_PQ4,
TEGRA_PIN_KB_COL5_PQ5,
TEGRA_PIN_KB_COL6_PQ6,
};
static const unsigned lcsn_pins[] = {
TEGRA_PIN_LCD_CS0_N_PN4,
};
static const unsigned ld0_pins[] = {
TEGRA_PIN_LCD_D0_PE0,
};
static const unsigned ld1_pins[] = {
TEGRA_PIN_LCD_D1_PE1,
};
static const unsigned ld2_pins[] = {
TEGRA_PIN_LCD_D2_PE2,
};
static const unsigned ld3_pins[] = {
TEGRA_PIN_LCD_D3_PE3,
};
static const unsigned ld4_pins[] = {
TEGRA_PIN_LCD_D4_PE4,
};
static const unsigned ld5_pins[] = {
TEGRA_PIN_LCD_D5_PE5,
};
static const unsigned ld6_pins[] = {
TEGRA_PIN_LCD_D6_PE6,
};
static const unsigned ld7_pins[] = {
TEGRA_PIN_LCD_D7_PE7,
};
static const unsigned ld8_pins[] = {
TEGRA_PIN_LCD_D8_PF0,
};
static const unsigned ld9_pins[] = {
TEGRA_PIN_LCD_D9_PF1,
};
static const unsigned ld10_pins[] = {
TEGRA_PIN_LCD_D10_PF2,
};
static const unsigned ld11_pins[] = {
TEGRA_PIN_LCD_D11_PF3,
};
static const unsigned ld12_pins[] = {
TEGRA_PIN_LCD_D12_PF4,
};
static const unsigned ld13_pins[] = {
TEGRA_PIN_LCD_D13_PF5,
};
static const unsigned ld14_pins[] = {
TEGRA_PIN_LCD_D14_PF6,
};
static const unsigned ld15_pins[] = {
TEGRA_PIN_LCD_D15_PF7,
};
static const unsigned ld16_pins[] = {
TEGRA_PIN_LCD_D16_PM0,
};
static const unsigned ld17_pins[] = {
TEGRA_PIN_LCD_D17_PM1,