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Commits on Apr 9, 2014

• [NVPTX] Add preliminary intrinsics and codegen support for textures/surfaces

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• [NVPTX] Add support for addrspacecast in global variable initializers, including emitting generic() when casting to address space 0.

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• [NVPTX] Add query support for read-write images and managed variables

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• Fix some doc and comment typos

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  atoker

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• [ARM64] Change SYS without a register to an alias to make disassembling more consistant.

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  brads55

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• [ARM64] Correctly disassemble ISB operand as ISB not DBarrier.

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• [ARM64] Properly support both apple and standard syntax for FMOV

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• [ARM64] Flag setting logical/add/sub immediate instructions don't use SP.

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• [ARM64] Conditional branches must always print their condition code, even AL.

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• [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.

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• [ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional.

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• [ARM64] Add missing shifted register MVN alias to ORN

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• [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.

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• [ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a dumb alias.

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• [ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all labels types

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• [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.

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• [ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions.

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• [ARM64] Rename LR to the UAL-compliant 'X30'.

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• [ARM64] Rename FP to the UAL-compliant 'X29'.

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• [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be zero but should be decoded/disassembled with any value.

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• [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.

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• [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top bit of their immediate clear.

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• [ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero.

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• [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.

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• [ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu.

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• [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.

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• [ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.

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• [ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.

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• [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value.

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• [ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disassembly.

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• [ARM64] Remove PrefetchOp and use ARM64PRFM instead.

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• [ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway.

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• [ARM64] Remove ARM64SYS.

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• [ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS.

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• [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process.

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