README-Verilog.md

This is a most popular repository list for Verilog sorted by number of stars

STARS	FORKS	ISSUES	LAST COMMIT	NAME/PLACE	DESCRIPTION
1812	808	33	4 months ago	e200_opensource/1	Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
1719	467	36	1 year, 3 months ago	picorv32/2	PicoRV32 - A Size-Optimized RISC-V CPU
1330	447	25	4 days ago	wujian100_open/3	IC design and development should be faster，simpler and more reliable
1155	182	11	4 months ago	darkriscv/4	opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
1114	436	186	3 years ago	hw/5	RTL, Cmodel, and testbench for NVDLA
946	69	2	2 years ago	amiga2000-gfxcard/6	MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog
839	284	43	3 days ago	verilog-ethernet/7	Verilog Ethernet components for FPGA implementation
806	1090	18	4 months ago	hdl/8	HDL libraries and projects
703	80	2	9 hours ago	zipcpu/9	A small, light weight, RISC CPU soft core
679	183	10	3 years ago	miaow/10	An open source GPU based off of the AMD Southern Islands ISA.
646	145	35	18 hours ago	corundum/11	Open source, high performance, FPGA-based NIC
634	219	30	a day ago	oh/12	Verilog library for ASIC and FPGA designers
589	47	18	7 hours ago	learn-fpga/13	Learning FPGA, yosys, nextpnr, and RISC-V
583	487	54	18 days ago	uhd/14	The USRP™ Hardware Driver Repository
561	280	7	2 years ago	ODriveHardware/15	High performance motor control
500	156	4	1 year, 3 months ago	open-fpga-verilog-tutorial/16	Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
459	82	13	29 days ago	serv/17	SERV - The SErial RISC-V CPU
446	80	2	1 year, 6 months ago	LeFlow/18	Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
439	168	1	3 years ago	mips-cpu/19	MIPS CPU implemented in Verilog
438	69	37	7 minutes ago	microwatt/20	A tiny Open POWER ISA softcore written in VHDL 2008
432	95	35	a day ago	sd2snes/21	SD card based multi-purpose cartridge for the SNES
427	156	9	15 hours ago	verilog-axi/22	Verilog AXI components for FPGA implementation
378	126	63	5 hours ago	OpenLane/23	OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
371	123	45	29 minutes ago	OpenROAD/24	OpenROAD's unified application implementing an RTL-to-GDS Flow
352	74	18	9 months ago	riscv-formal/25	RISC-V Formal Verification Framework
345	174	39	4 years ago	riffa/26	The RIFFA development repository
344	77	4	1 year, 3 months ago	riscv/27	RISC-V CPU Core (RV32IM)
342	125	25	15 days ago	mor1kx/28	mor1kx - an OpenRISC 1000 processor IP core
339	159	1	6 years ago	FPGA-Imaging-Library/29	An open source library for image processing on FPGA.
327	104	0	5 days ago	basic_verilog/30	Must-have verilog systemverilog modules
323	116	0	3 years ago	verilog/31	Repository for basic (and not so basic) Verilog blocks with high re-use potential
311	12	4	26 days ago	graphics-gremlin/32	Open source retro ISA video card
307	120	3	a month ago	cores/33	Various HDL (Verilog) IP Cores
307	107	9	22 hours ago	verilog-pcie/34	Verilog PCI express components
304	41	10	6 months ago	VerilogBoy/35	A Pi emulating a GameBoy sounds cheap. What about an FPGA?
289	94	7	2 years ago	icezum/36	🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board
284	132	14	9 years ago	netfpga/37	NetFPGA 1G infrastructure and gateware
281	26	69	5 months ago	ucr-eecs168-lab/38	The lab schedules for EECS168 at UC Riverside
277	54	6	15 days ago	biriscv/39	32-bit Superscalar RISC-V CPU
271	54	1	11 hours ago	step_into_mips/40	一步一步写MIPS CPU
261	117	18	3 years ago	convolution_network_on_FPGA/41	CNN acceleration on virtex-7 FPGA with verilog HDL
258	119	6	7 years ago	FPGA-Litecoin-Miner/42	A litecoin scrypt miner implemented with FPGA on-chip memory.
253	36	8	a month ago	Project-Zipline/43	Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.
246	92	25	8 days ago	OpenTimer/44	A High-performance Timing Analysis Tool for VLSI Systems
245	36	7	7 days ago	Flute/45	RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
238	86	12	a month ago	fpu/46	synthesiseable ieee 754 floating point library in verilog
233	27	21	1 year, 10 months ago	spispy/47	An open source SPI flash emulator and monitor
232	96	0	15 days ago	openwifi-hw/48	FPGA/hardware design of openwifi
231	55	2	3 years ago	zet/49	Open source implementation of a x86 processor
229	70	1	9 months ago	verilog-6502/50	A Verilog HDL model of the MOS 6502 CPU
217	40	13	a month ago	Piccolo/51	RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
217	44	9	a month ago	litepcie/52	Small footprint and configurable PCIe core
209	37	1	a month ago	wb2axip/53	Bus bridges and other odds and ends
204	54	22	9 years ago	fpga_nes/54	FPGA-based Nintendo Entertainment System Emulator
204	44	1	4 years ago	ridecore/55	RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
197	68	13	8 months ago	Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/56	Verilog Generator of Neural Net Digit Detector for FPGA
197	81	3	a month ago	verilog-i2c/57	Verilog I2C interface for FPGA implementation
197	48	138	10 hours ago	basejump_stl/58	BaseJump STL: A Standard Template Library for SystemVerilog
192	70	3	3 years ago	CNN-FPGA/59	使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用
191	71	5	6 months ago	verilog-uart/60	Verilog UART
188	69	1	1 year, 8 months ago	AccDNN/61	A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
184	181	0	29 days ago	fpga/62	The USRP™ Hardware Driver FPGA Repository
183	60	3	2 months ago	e203_hbirdv2/63	The Ultra-Low Power RISC-V Core
182	68	1	4 years ago	sdram-controller/64	Verilog SDRAM memory controller
179	86	0	16 days ago	Kryon/65	FPGA,Verilog,Python
179	29	6	3 years ago	TinyFPGA-B-Series/66	Open source design files for the TinyFPGA B-Series boards.
178	38	3	20 days ago	fpga_readings/67	Recipe for FPGA cooking
173	63	2	2 months ago	sha256/68	Hardware implementation of the SHA-256 cryptographic hash function
171	8	1	2 years ago	fpga-chip8/69	CHIP-8 console on FPGA
171	67	0	a month ago	Verilog-Practice/70	HDLBits website practices & solutions
169	45	6	11 days ago	icesugar/71	iCESugar FPGA Board (base on iCE40UP5k)
167	21	0	7 years ago	ez8/72	The Easy 8-bit Processor
166	67	3	a day ago	SCALE-MAMBA/73	Repository for the SCALE-MAMBA MPC system
163	22	6	a month ago	twitchcore/74	It's a core. Made on Twitch.
161	10	0	1 year, 9 months ago	fpg1/75	PDP-1 FPGA implementation in Verilog, with CRT, Teletype and Console.
159	29	2	a month ago	ice40-playground/76	Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)
155	78	0	2 months ago	aes/77	Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
151	84	5	6 months ago	openofdm/78	Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
149	39	4	9 months ago	nandland/79	All code found on nandland is here. underconstruction.gif
149	27	0	2 years ago	SimpleVOut/80	A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
145	38	0	6 months ago	wbuart32/81	A simple, basic, formally verified UART controller
139	27	6	2 years ago	DisplayPort_Verilog/82	A Verilog implementation of DisplayPort protocol for FPGAs
139	46	5	2 years ago	Tang_E203_Mini/83	LicheeTang 蜂鸟E203 Core
138	29	4	1 year, 9 months ago	FPGA-peripherals/84	🌱 ❄️ Collection of open-source peripherals in Verilog
138	46	22	1 year, 9 months ago	open-register-design-tool/85	Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
132	72	3	4 years ago	FPGA_Based_CNN/86	FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
131	45	1	10 months ago	schoolMIPS/87	CPU microarchitecture, step by step
130	39	0	7 years ago	milkymist/88	SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU
127	27	3	1 year, 9 months ago	raven-picorv32/89	Silicon-validated SoC implementation of the PicoSoc/PicoRV32
123	38	0	3 years ago	Single_instruction_cycle_OpenMIPS/90	通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
122	41	4	7 years ago	fpganes/91	NES in Verilog
121	42	0	1 year, 4 months ago	RePlAce/92	RePlAce global placement tool
120	33	0	5 hours ago	livehd/93	Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
120	82	4	8 years ago	uvm_axi/94	uvm AXI BFM(bus functional model)
120	31	1	10 months ago	iceGDROM/95	An FPGA based GDROM emulator for the Sega Dreamcast
118	12	0	3 years ago	vm80a/96	i8080 precise replica in Verilog, based on reverse engineering of real die
117	79	14	2 years ago	orpsoc-cores/97	Core description files for FuseSoC
117	16	3	a month ago	DreamcastHDMI/98	Dreamcast HDMI
115	23	3	8 days ago	a2o/99	None
115	36	56	4 days ago	symbiflow-examples/100	Example designs showing different ways to use SymbiFlow toolchains.
113	30	18	4 months ago	Cores-SweRVolf/101	FuseSoC-based SoC for SweRV EH1
112	75	5	3 years ago	Hardware-CNN/102	A convolutional neural network implemented in hardware (verilog)
112	23	0	4 years ago	archexp/103	浙江大学计算机体系结构课程实验
111	8	0	a month ago	fedar-f1-rv64im/104	5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.
111	23	1	1 year, 7 months ago	usbcorev/105	A full-speed device-side USB peripheral core written in Verilog.
107	31	0	3 years ago	mriscv/106	A 32-bit Microcontroller featuring a RISC-V core
106	7	2	2 months ago	icestation-32/107	Compact FPGA game console
106	48	63	a day ago	fomu-workshop/108	Support files for participating in a Fomu workshop
106	12	3	3 months ago	n64rgb/109	Everything around N64 and RGB
105	46	1	8 years ago	fft-dit-fpga/110	Verilog module for calculation of FFT.
103	16	3	6 months ago	panologic-g2/111	Pano Logic G2 Reverse Engineering Project
102	14	6	2 months ago	usb3_pipe/112	USB3 PIPE interface for Xilinx 7-Series / Lattice ECP5
102	15	1	4 months ago	cpu11/113	Revengineered ancient PDP-11 CPUs, originals and clones
101	36	33	a month ago	ao486_MiSTer/114	ao486 port for MiSTer
101	67	1	5 years ago	or1200/115	OpenRISC 1200 implementation
99	17	1	6 years ago	oldland-cpu/116	Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
98	23	0	1 year, 8 months ago	mips32-cpu/117	奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）
98	81	0	3 years ago	FPGA-CNN/118	FPGA implementation of Cellular Neural Network (CNN)
98	102	26	2 months ago	caravel/119	Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
98	19	5	1 year, 1 month ago	tinyfpga_bx_usbserial/120	USB Serial on the TinyFPGA BX
97	10	1	1 year, 1 month ago	lpc_sniffer_tpm/121	A low pin count sniffer for ICEStick - targeting TPM chips
96	8	0	11 months ago	vgasim/122	A Video display simulator
96	12	58	2 years ago	spatial-lang/123	Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
95	30	1	4 years ago	kamikaze/124	Light-weight RISC-V RV32IMC microcontroller core.
95	10	1	1 year, 3 months ago	antikernel/125	The Antikernel operating system project
95	18	1	1 year, 4 months ago	display_controller/126	FPGA display controller with support for VGA, DVI, and HDMI.
95	28	0	1 year, 7 months ago	NaiveMIPS-HDL/127	Naïve MIPS32 SoC implementation
93	37	9	1 year, 8 months ago	Tang_FPGA_Examples/128	LicheeTang FPGA Examples
92	35	0	3 days ago	ivtest/129	Regression test suite for Icarus Verilog.
92	9	3	a month ago	jt12/130	FM sound source written in Verilog, fully compatible with YM2612, YM3438 (JT12), YM2203 (JT03) and YM2610 (JT10)
91	36	8	2 years ago	mipsfpga-plus/131	MIPSfpga+ allows loading programs via UART and has a switchable clock
89	18	2	20 days ago	Toooba/132	RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
89	26	3	a month ago	icebreaker-verilog-examples/133	This repository contains small example designs that can be used with the open source icestorm flow.
89	19	4	6 years ago	NeoGeoHDMI/134	Verilog project that takes the digital video and audio from a Neo Geo MVS before going through the DACs and outputs the signals over HDMI
88	31	2	1 year, 4 days ago	apple-one/135	An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
87	40	4	5 months ago	vsdflow/136	VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
87	10	0	2 years ago	NeoGeoFPGA-sim/137	Simulation only cartridge NeoGeo hardware definition
86	11	0	5 years ago	PonyLink/138	A single-wire bi-directional chip-to-chip interface for FPGAs
86	9	1	3 years ago	iCE40/139	Lattice iCE40 FPGA experiments - Work in progress
86	20	0	1 year, 1 month ago	openarty/140	An Open Source configuration of the Arty platform
85	29	1	8 years ago	Xilinx-Serial-Miner/141	Bitcoin miner for Xilinx FPGAs
84	10	0	5 years ago	cpus-caddr/142	FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs
84	6	2	a month ago	vt52-fpga/143	None
84	48	35	9 days ago	Genesis_MiSTer/144	Sega Genesis for MiSTer
84	53	4	7 years ago	DSLogic-hdl/145	An open source FPGA design for DSLogic
83	30	42	29 days ago	Minimig-AGA_MiSTer/146	None
82	27	0	6 years ago	cpu/147	A very primitive but hopefully self-educational CPU in Verilog
82	21	1	1 year, 9 months ago	MobileNet-in-FPGA/148	Generator of verilog description for FPGA MobileNet implementation
82	18	1	3 months ago	ice40_ultraplus_examples/149	Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
81	8	1	10 years ago	Homotopy/150	Homotopy theory in Coq.
81	12	3	4 years ago	fpgaboy/151	Implementation Nintendo's GameBoy console on an FPGA
81	25	0	6 years ago	lm32/152	LatticeMico32 soft processor
81	21	7	1 year, 2 months ago	ice40_examples/153	Public examples of ICE40 HX8K examples using Icestorm
80	22	15	3 years ago	c65gs/154	FPGA-based C64 Accelerator / C65 like computer
80	13	0	1 year, 5 months ago	agc_simulation/155	Verilog simulation files for a replica of the Apollo Guidance Computer
78	44	3	8 years ago	Icarus/156	DUAL Spartan6 Development Platform
76	20	1	24 minutes ago	aib-phy-hardware/157	Advanced Interface Bus (AIB) die-to-die hardware open source
76	32	65	9 days ago	bsg_manycore/158	Tile based architecture designed for computing efficiency, scalability and generality
76	51	2	a day ago	LimeSDR-USB_GW/159	Altera Cyclone IV FPGA project for the USB 3.0 LimeSDR board
75	9	5	7 days ago	VGChips/160	Video Game custom chips reverse-engineered from silicon
75	14	2	1 year, 11 months ago	MIPS-pipeline-processor/161	A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
75	18	5	1 year, 11 months ago	Reindeer/162	PulseRain Reindeer - RISCV RV32I[M] Soft CPU
73	7	1	9 months ago	core_jpeg/163	High throughput JPEG decoder in Verilog for FPGA
73	39	0	8 years ago	uart/164	Verilog UART
73	28	0	2 years ago	PASC/165	Parallel Array of Simple Cores. Multicore processor.
72	28	1	3 years ago	clacc/166	Deep Learning Accelerator (Convolution Neural Networks)
72	31	9	8 months ago	c5soc_opencl/167	DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.
72	41	32	3 days ago	NeoGeo_MiSTer/168	NeoGeo for MiSTer
71	19	1	3 months ago	dspfilters/169	A collection of demonstration digital filters
71	17	1	3 years ago	RISC-V-CPU/170	RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
71	14	0	3 months ago	Colorlight-FPGA-Projects/171	current focus on Colorlight i5 series module
70	19	2	2 years ago	ZAP/172	ZAP is a pipelined ARMv4T architecture compatible processor with cache and MMU.
70	29	1	3 years ago	verilog-lfsr/173	Fully parametrizable combinatorial parallel LFSR/CRC module
69	2	0	2 months ago	riskow/174	Learning how to make a RISC-V
69	10	8	4 months ago	xcrypto/175	XCrypto: a cryptographic ISE for RISC-V
68	8	7	2 days ago	jt_gng/176	CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter, Vulgus and The Speed Rumbler.
68	23	1	3 years ago	SoftMC/177	SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies" https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17.pdf
67	33	0	4 months ago	cdbus_ip/178	CDBUS Protocol and the IP Core for FPGA users
67	30	0	3 months ago	async_fifo/179	A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
66	13	0	2 years ago	toygpu/180	A simple GPU on a TinyFPGA BX
66	23	1	2 months ago	Haasoscope/181	Docs, design, firmware, and software for the Haasoscope
64	26	3	3 years ago	VidorFPGA/182	repository for Vidor FPGA IP blocks and projects
64	53	5	3 years ago	Convolutional-Neural-Network/183	Implementation of CNN using Verilog
63	14	3	9 years ago	ao68000/184	The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.
63	25	0	4 months ago	DetectHumanFaces/185	Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
63	32	1	3 years ago	zynq-axis/186	Hardware, Linux Driver and Library for the Zynq AXI DMA interface
63	31	3	7 months ago	SD-card-controller/187	WISHBONE SD Card Controller IP Core
63	8	0	4 years ago	FPGA-TX/188	FPGA based transmitter
63	12	0	2 years ago	MARLANN/189	Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
62	30	0	3 months ago	cdpga/190	FPGA core boards / evaluation boards based on CDCTL hardware
62	38	3	28 days ago	blinky/191	Example LED blinking project for your FPGA dev board of choice
61	20	2	1 year, 4 months ago	h265-encoder-rtl/192	None
61	29	2	1 year, 13 days ago	cnn_hardware_acclerator_for_fpga/193	This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs
61	53	1	9 months ago	Practical-UVM-Step-By-Step/194	This is the main repository for all the examples for the book Practical UVM
60	9	1	1 year, 9 months ago	Riscy-SoC/195	Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
60	14	0	2 years ago	riscv/196	Verilog implementation of a RISC-V core
59	28	5	2 months ago	libsystemctlm-soc/197	SystemC/TLM-2.0 Co-simulation framework
59	35	20	15 days ago	Gameboy_MiSTer/198	Gameboy for MiSTer
59	13	0	2 years ago	hyperram/199	Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
59	26	0	3 years ago	mnist_fpga/200	using xilinx xc6slx45 to implement mnist net
59	12	0	8 months ago	mc6809/201	Cycle-Accurate MC6809/E implementation, Verilog
58	5	0	8 months ago	rt/202	A Full Hardware Real-Time Ray-Tracer
58	25	2	1 year, 10 months ago	daisho/203	Test of the USB3 IP Core from Daisho on a Xilinx device
58	24	2	11 months ago	core_ddr3_controller/204	A DDR3 memory controller in Verilog for various FPGAs
56	19	0	6 years ago	Verilog-caches/205	Various caches written in Verilog-HDL
55	31	8	4 years ago	nysa-sata/206	None
55	21	0	9 months ago	SM3_core/207	None
55	16	0	1 year, 2 months ago	hardenedlinux_profiles/208	It contains hardenedlinux community documentation.
55	6	2	1 year, 8 months ago	ay-3-8910_reverse_engineered/209	The reverse-engineered AY-3-8910 chip. Transistor-level schematics, verilog model and a testbench with tools, that can render register dump files into .flac soundtrack.
54	17	0	7 years ago	verilog_fixed_point_math_library/210	Fixed Point Math Library for Verilog
54	13	1	6 months ago	sdspi/211	SD-Card controller, using a SPI interface that is (optionally) shared
54	11	1	2 months ago	up5k/212	Upduino v2 with the ice40 up5k FPGA demos
53	3	0	6 months ago	wbscope/213	A wishbone controlled scope for FPGA's
53	10	4	9 months ago	amiga_replacement_project/214	This is an attempt to make clean Verilog sources for each chip on the Amiga.
53	14	0	5 years ago	fpga-md5-cracker/215	A 64-stage pipelined MD5 implementation written in verliog. Runs reliably on a DE0-Nano at 100mhz, computing 100 million hashes per second.
53	20	13	1 year, 10 months ago	alpha-release/216	Builds, flow and designs for the alpha release
53	4	1	7 months ago	xenowing/217	"What comes next? Super Mario 128? Actually, that's what I want to do."
52	25	0	11 months ago	timetoexplore/218	Source code to accompany https://timetoexplore.net
52	22	1	3 months ago	opencpi/219	Open Component Portability Infrastructure
52	25	5	21 hours ago	vortex/220	None
52	5	0	2 months ago	vdatp/221	Volumetric Display using an Acoustically Trapped Particle
52	18	2	2 years ago	Verilog-Projects/222	This repository contains source code for past labs and projects involving FPGA and Verilog based designs
52	2	0	2 years ago	soc/223	An experimental System-on-Chip with a custom compiler toolchain.
52	31	36	5 years ago	minimig-mist/224	Minimig for the MiST board
52	14	0	2 years ago	VexRiscvSoftcoreContest2018/225	None
51	7	0	2 years ago	up5k_basic/226	A small 6502 system with MS BASIC in ROM
51	38	0	6 years ago	IPCORE/227	None
51	5	1	1 year, 6 months ago	flickerfixer/228	An open source flicker fixer for Amiga 500/2000
51	18	1	1 year, 6 months ago	aib-phy-hardware/229	None
51	11	0	9 months ago	screen-pong/230	Pong game in a FPGA.
51	7	13	2 years ago	Neogeo_MiSTer_old/231	SNK NeoGeo core for the MiSTer platform
51	23	1	3 years ago	TOE/232	TCP Offload Engine
51	11	0	1 year, 12 days ago	XilinxUnisimLibrary/233	None
51	19	0	3 years ago	MIPS/234	A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
51	17	3	9 years ago	ORGFXSoC/235	An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)
51	11	0	1 year, 7 months ago	icebreaker-workshop/236	iCEBreaker Workshop
51	12	1	1 year, 1 month ago	challenges-2020/237	Pwn2Win 2020 Challenges
50	22	0	1 year, 9 months ago	R8051/238	8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
50	27	3	4 years ago	digital-servo/239	NIST digital servo: an FPGA based fast digital feedback controller
50	34	1	6 years ago	mips32r1_xum/240	A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. This is a bare-metal CPU with no virtual memory. (Old University of Utah XUM archive)
50	6	47	10 months ago	rigel/241	Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
49	16	0	2 years ago	BUAA_CO/242	2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)
48	41	0	1 year, 8 months ago	AMBA_AXI_AHB_APB/243	AMBA bus lecture material
48	8	1	1 year, 9 months ago	panologic/244	PanoLogic Zero Client G1 reverse engineering info
48	3	1	1 year, 4 months ago	gameboy-fpga-cartridge/245	None
47	7	15	5 months ago	hrm-cpu/246	Human Resource Machine - CPU Design #HRM
47	27	1	4 years ago	h.265_encoder/247	None
47	3	1	4 years ago	21FX/248	A bootloader for the SNES console
47	20	6	27 days ago	corescore/249	CoreScore
47	26	2	2 years ago	verilog-cam/250	Verilog Content Addressable Memory Module
47	10	3	2 months ago	OpenAmiga500FastRamExpansion/251	4/8 MB Fast RAM Expansion for the Commodore Amiga 500
46	26	2	7 years ago	beagle/252	BeagleBone HW, SW, & FPGA Development
46	6	1	3 years ago	lpc_sniffer/253	a low pin count sniffer for icestick
46	3	0	3 years ago	collection-iPxs/254	Icestudio Pixel Stream collection
46	13	1	1 year, 3 months ago	fpga-sdft/255	sliding DFT for FPGA, targetting Lattice ICE40 1k
46	21	0	2 years ago	NPU_on_FPGA/256	在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。
45	24	25	9 days ago	MegaCD_MiSTer/257	Mega CD for MiSTer
45	7	1	26 days ago	icesugar-pro/258	iCESugar series FPGA dev board
45	9	4	8 months ago	ice-chips-verilog/259	IceChips is a library of all common discrete logic devices in Verilog
45	17	2	3 years ago	chiphack/260	Repository and Wiki for Chip Hack events.
45	13	0	3 years ago	caribou/261	Caribou: Distributed Smart Storage built with FPGAs
44	6	0	4 years ago	MAM65C02-Processor-Core/262	Microprogrammed 65C02-compatible FPGA Processor Core (Verilog-2001)
44	36	1	2 years ago	AlteraDE2Labs_Verilog/263	My solutions to Alteras example labs
44	16	0	8 years ago	Multiplier16X16/264	Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
44	17	0	1 year, 2 months ago	max1000-tutorial/265	Tutorial and example projects for the Arrow MAX1000 FPGA board
44	14	0	5 years ago	yarvi/266	Yet Another RISC-V Implementation
44	8	0	a month ago	Fuxi/267	Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
44	28	1	2 years ago	GNSS_Firehose/268	Wideband front-end digitizer for GPS, GLONASS, Galileo, BeiDou
44	11	1	13 days ago	benchmarks/269	EPFL logic synthesis benchmarks
44	6	1	11 months ago	iua/270	ice40 USB Analyzer
44	14	0	4 years ago	sds7102/271	A port of Linux to the OWON SDS7102 scope
43	30	0	5 years ago	mojo-base-project/272	This is the base project for the Mojo. It should be used as the starting point for all projects.
43	32	1	3 years ago	ethernet_10ge_mac_SV_UVM_tb/273	SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
43	10	0	3 years ago	mips-cpu/274	A MIPS CPU implemented in Verilog
43	13	1	a month ago	sha3/275	None
43	5	1	2 years ago	engine-V/276	SoftCPU/SoC engine-V
43	18	1	3 years ago	ARM7/277	Implemetation of pipelined ARM7TDMI processor in Verilog
43	16	0	1 year, 7 months ago	drec-fpga-intro/278	Materials for "Introduction to FPGA and Verilog" at MIPT DREC
42	9	0	2 years ago	ctf/279	Stuff from CTF contests
42	11	3	10 days ago	SOFA/280	SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
42	11	1	2 years ago	Speech256/281	An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.
42	39	6	a day ago	OpenROAD-flow-scripts/282	None
42	27	3	3 years ago	prog_fpgas/283	The repository for the Verilog code examples and ISE projects that accompany the book Programming FPGAs: Getting Started with Verilog.
42	15	0	18 days ago	dpll/284	A collection of phase locked loop (PLL) related projects
42	31	3	5 years ago	bch_verilog/285	Verilog based BCH encoder/decoder
41	11	0	2 years ago	DIY_OpenMIPS/286	實作《自己動手寫CPU》書上的程式碼
41	15	48	8 days ago	tapasco/287	The Task Parallel System Composer (TaPaSCo)
41	9	0	1 year, 29 days ago	moxie-cores/288	Moxie-compatible core repository
41	7	0	2 years ago	fpga-odysseus/289	FPGA Odysseus with ULX3S
41	9	1	3 years ago	BAR-Tender/290	An FPGA I/O Device which services physical memory reads/writes via UMDF2 driver
40	14	2	2 years ago	BeagleWire/291	This repository contains software for BeagleWire. It is a realization of my project for GSOC-2017
40	8	2	2 years ago	cnnhwpe/292	None
40	42	1	4 days ago	oc-accel/293	OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
40	9	2	7 months ago	basic-ecp5-pcb/294	Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs
40	5	2	4 years ago	Frix/295	IBM PC Compatible SoC for a commercially available FPGA board
40	6	0	2 months ago	UltraMIPS_NSCSCC/296	UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
40	6	1	14 days ago	GottaGoFastRAM/297	8MB Autoconfig FastRAM for Amiga 500/1000/2000/CDTV
39	16	0	1 year, 10 months ago	ethmac/298	Ethernet MAC 10/100 Mbps
39	8	2	4 years ago	ACC/299	Apollo CPU Core in Verilog. For learning and having fun with open FPGA
39	4	0	2 years ago	tiny_usb_examples/300	Using the TinyFPGA BX USB code in user designs
39	12	0	a year ago	first-fpga-pcb/301	FPGA dev board based on Lattice iCE40 8k
39	29	3	7 years ago	cordic/302	An implementation of the CORDIC algorithm in Verilog.
38	6	0	1 year, 3 months ago	MIPS48PipelineCPU/303	5 stage pipelined MIPS-32 processor
38	3	0	10 months ago	sdram-controller/304	Generic FPGA SDRAM controller, originally made for AS4C4M16SA
38	11	0	2 years ago	HyperBUS/305	A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
38	15	3	4 months ago	verilog-math/306	Mathematical Functions in Verilog
38	5	0	3 years ago	Computer-Architecture-Task-2/307	Riscv32 CPU Project
38	27	0	9 years ago	DDR2_Controller/308	DDR2 memory controller written in Verilog
37	15	1	2 years ago	FPGA-Accelerator-for-AES-LeNet-VGG16/309	FPGA/AES/LeNet/VGG16
37	17	1	18 years ago	8051/310	8051 core
37	22	1	8 years ago	Atalanta/311	Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
37	14	0	3 years ago	robot-arm-v01/312	None
37	10	2	4 months ago	iceZ0mb1e/313	FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC
36	10	1	5 years ago	oc_jpegencode/314	Fork of OpenCores jpegencode with Cocotb testbench
36	15	3	5 years ago	FPU/315	IEEE 754 floating point unit in Verilog
36	14	4	1 year, 2 months ago	i3c-slave-design/316	MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
36	1	1	5 months ago	spokefpga/317	FPGA Tools and Library
36	9	0	9 years ago	dcpu16/318	Pipelined DCPU-16 Verilog Implementation
36	13	0	4 years ago	ECE1373_2016_hft_on_fpga/319	High Frequency Trading using Vivado HLS
36	4	0	3 years ago	RISC-processor/320	Simple single cycle RISC processor written in Verilog
36	20	0	2 years ago	huaweicloud-fpga/321	The official repository of the HUAWEI CLOUD FPGA Development Kit based on HUAWEI CLOUD FPGA Accelerated Cloud Server.
36	13	1	1 year, 8 months ago	Open_RegModel/322	🐥Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
36	21	1	3 years ago	OV7670-Verilog/323	Verilog modules required to get the OV7670 camera working
35	2	0	3 years ago	vga_to_ascii/324	Realtime VGA to ASCII Art converter
35	13	0	5 years ago	yosys-bigsim/325	A collection of big designs to run post-synthesis simulations with yosys
35	7	5	7 months ago	74xx-liberty/326	None
35	29	7	2 years ago	spi-slave/327	SPI Slave for FPGA in Verilog and VHDL
35	2	0	5 months ago	fpga_pio/328	An attempt to recreate the RP2040 PIO in an FPGA
35	19	1	5 years ago	nfmac10g/329	Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
35	15	1	6 years ago	minimig-de1/330	Minimig for the DE1 board
35	14	0	1 year, 1 month ago	neuralNetwork/331	None
34	0	0	2 years ago	comparchitecture/332	Verilog and MIPS simple programs
34	12	41	22 days ago	zx-evo/333	TS-Configuration for ZX Spectrum clone named ZX-Evolution
34	11	0	9 months ago	trng/334	True Random Number Generator core implemented in Verilog.
34	7	0	5 months ago	EDN8-PRO/335	EverDrive N8 PRO dev sources
34	12	0	1 year, 4 months ago	MIPS-Processor/336	5-stage pipelined 32-bit MIPS microprocessor in Verilog
33	16	0	6 years ago	verilog-utils/337	native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
33	13	3	2 years ago	HDL-Bits-Solutions/338	This is a repository containing solutions to the problem statements given in HDL Bits website.
33	8	0	10 months ago	Solutions-to-HDLbits-Verilog-sets/339	Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).
33	2	0	5 years ago	HaSKI/340	Cλash/Haskell FPGA-based SKI calculus evaluator
33	6	0	11 months ago	core_dvi_framebuffer/341	Minimal DVI / HDMI Framebuffer
33	5	0	10 days ago	ZYNQ-NVDLA/342	NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
33	21	0	9 months ago	thinpad_top/343	Project template for Artix-7 based Thinpad board
33	11	0	1 year, 2 months ago	LUTNet/344	None
33	6	0	4 years ago	wiki/345	None
33	13	0	8 years ago	fpganes/346	FPGA-based AI for Super Mario Bros. Designed for an Altera DE2
33	11	0	2 months ago	MangoMIPS32/347	A softcore microprocessor of MIPS32 architecture.
33	15	1	2 years ago	ARM-LEGv8/348	Verilog Implementation of an ARM LEGv8 CPU
32	13	1	9 years ago	vSPI/349	Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter
32	21	1	3 years ago	fpga_design/350	这是我所开发的两个项目，包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统
32	11	0	2 years ago	csirx/351	Open-source CSI-2 receiver for Xilinx UltraScale parts
32	4	1	5 months ago	vga-clock/352	Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
32	15	0	2 years ago	8-bits-RISC-CPU-Verilog/353	Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
32	12	0	1 year, 5 months ago	SIGMA/354	RTL implementation of Flex-DPE.
32	2	0	6 years ago	gb/355	The Original Nintendo Gameboy in Verilog
32	3	6	5 months ago	QuokkaEvaluation/356	Example projects for Quokka FPGA toolkit
32	12	0	2 months ago	sha1/357	Verilog implementation of the SHA-1 cryptgraphic hash function
31	54	2	2 months ago	iob-soc/358	RISC-V System on Chip Template Based on the picorv32 Processor
31	24	4	4 months ago	Menu_MiSTer/359	None
31	9	0	2 years ago	tiny-tpu/360	Small-scale Tensor Processing Unit built on an FPGA
31	8	0	1 year, 3 days ago	RDF-2019/361	DATC RDF
31	6	0	3 years ago	OpenFPGA/362	OpenFPGA
31	9	0	6 years ago	vj-uart/363	Virtual JTAG UART for Altera Devices
31	14	3	3 years ago	Processor-UVM-Verification/364	System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
31	17	0	9 years ago	verilog-sha256/365	Implementation of the SHA256 Algorithm in Verilog
31	3	3	1 year, 2 months ago	observer/366	None
31	6	0	14 days ago	verilog-65C02/367	65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface
31	4	3	23 hours ago	snark-barker-mca/368	A Sound Blaster compatible sound card for Micro Channel bus computers
31	5	0	6 months ago	sdr/369	A basic Soft(Gate)ware Defined Radio architecture
31	19	1	2 years ago	GnuRadar/370	Open-source software defined radar based on the USRP 1 hardware.
31	8	39	19 days ago	mantle/371	mantle library
31	20	7	21 days ago	Template_MiSTer/372	Template with latest framework for MiSTer
31	2	1	2 years ago	icebreaker-candy/373	Eye candy from an iCEBreaker FPGA and a 64×64 LED panel
31	25	0	3 years ago	Examples-in-book-write-your-own-cpu/374	《自己动手写CPU》一书附带的文件
30	15	0	3 years ago	eddr3/375	mirror of https://git.elphel.com/Elphel/eddr3
30	13	2	11 years ago	round_robin_arbiter/376	round robin arbiter
30	6	2	1 year, 6 months ago	datc_robust_design_flow/377	DATC Robust Design Flow.
30	12	1	1 year, 5 months ago	Tang-Nano-examples/378	Tang-Nano-examples
30	6	0	1 year, 6 months ago	icestick-glitcher/379	Simple voltage glitcher implementation for the Lattice iCEstick Evaluation Kit
30	13	2	3 years ago	CNN_VGG19_verilog/380	Convolution Neural Network of vgg19 model in verilog
29	2	0	2 years ago	riscv-megaproject/381	A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earlier ones
29	4	2	9 months ago	zbasic/382	A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
29	12	0	5 years ago	stx_cookbook/383	Altera Advanced Synthesis Cookbook 11.0
29	13	1	3 years ago	openmsp430/384	The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
29	5	0	4 hours ago	SiDi-FPGA/385	SiDi FPGA for retro systems.
29	34	0	7 years ago	FPGA_image_processing/386	Image capture, image filtering and image display (VGA) : picture in picture, edge detection, gray image and smooth image
29	7	5	7 months ago	icestick-lpc-tpm-sniffer/387	FPGA-based LPC bus sniffing tool for Lattice iCEstick Evaluation Kit
29	19	0	2 years ago	x393/388	mirror of https://git.elphel.com/Elphel/x393
29	4	1	a month ago	A500_ACCEL_RAM_IDE-Rev-2/389	Improved design attempt for Amiga 500 in socket 68000 Accelerator, FastRAM and IDE Interface
29	13	0	1 year, 8 months ago	spi_mem_programmer/390	Small (Q)SPI flash memory programmer in Verilog
29	7	2	2 years ago	iCEstick-UART-Demo/391	This is a simple UART echo test for the iCEstick Evaluation Kit
29	17	0	2 years ago	de10nano_vgaHdmi_chip/392	Test for video output using the ADV7513 chip on a de10 nano board
29	3	1	5 years ago	RISCV_Piccolo_v1/393	Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
29	12	13	2 days ago	DFFRAM/394	Standard Cell Library based Memory Compiler using DFF cells
29	9	1	a day ago	jtframe/395	Common framework for MiST(er), SiDi, ZX-UNO/DOS and Unamiga core development. With special focus on arcade cores.
29	2	0	1 year, 6 months ago	cisco-hwic-3g-cdma/396	Reverse Engineering of the Cisco HWIC-3G-CDMA PCB
29	7	0	10 months ago	avr/397	Reads a state transition system and performs property checking
29	3	0	7 years ago	CPU32/398	Tiny MIPS for Terasic DE0
28	9	0	8 years ago	lsasim/399	Educational load/store instruction set architecture processor simulator
28	3	0	3 years ago	s6soc/400	CMod-S6 SoC
28	12	2	Unknown	xfcp/401	Extensible FPGA control platform
28	9	1	Unknown	Basic-SIMD-Processor-Verilog-Tutorial/402	Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
28	18	0	Unknown	tdc-core/403	A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs
28	22	0	Unknown	opensketch/404	simulation and netfpga code
27	15	0	Unknown	HitchHike/405	None
27	21	0	Unknown	fast/406	FAST
27	17	2	Unknown	Hardware-Implementation-of-AES-Verilog/407	Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog
27	0	0	Unknown	cxxrtl_eval/408	Experiments with Yosys cxxrtl backend
27	5	1	Unknown	Lichee-Tang/409	Lichee Tang FPGA board examples
27	9	2	Unknown	Posit-HDL-Arithmetic/410	Universal number Posit HDL Arithmetic Architecture generator
27	11	1	Unknown	ARM_Cortex-M3/411	该项目依据全国大学生集成电路创新创业大赛“ARM杯”赛题要求，在FPGA上搭建Cortex-M3软核、图像协处理器，并通过OV5640摄像头采集车牌图像，实现对车牌的识别与结果显示。项目基于Altera DE1 FPGA搭载Cortex-M3软核，依据AHB-Lite总线协议，将LCD1602、RAM、图像协处理器等外设挂载至Cortex-M3。视频采集端，设计写FiFo模块、SDRAM存储与输出、读FiFo模块、灰度处理模块、二值化、VGA显示等模块。最终将400位宽的结果数据（对应20张车牌）存储在RAM中，输出至AHB总线，由Cortex-M3调用并显示识别结果。
27	7	0	Unknown	LVDS-7-to-1-Serializer/412	An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.
27	13	0	Unknown	FPGA_Ultrasound/413	CMU 18545 FPGA project -- Multi-channel ultrasound data acquisition and beamforming system.
27	16	2	Unknown	ARM9-compatible-soft-CPU-core/414	This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
27	10	0	Unknown	Spartan-Mini-NES/415	An FPGA based handheld NES system built around the Spartan 6 and the Spartan Mini development board.
27	6	3	Unknown	v-regex/416	A simple regex library for V
27	17	5	Unknown	ODIN/417	ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.
27	23	0	Unknown	AES-FPGA/418	AES加密解密算法的Verilog实现
27	11	0	Unknown	qspiflash/419	A set of Wishbone Controlled SPI Flash Controllers
27	6	4	Unknown	OpenCGRA/420	OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
27	31	0	Unknown	jtag_vpi/421	TCP/IP controlled VPI JTAG Interface.
27	9	3	Unknown	Nitro-Parts-lib-Xilinx/422	This is mainly a simulation library of xilinx primitives that are verilator compatible.
27	16	0	Unknown	rfid-verilog/423	RFID tag and tester in Verilog
27	9	0	Unknown	Open-FPGA/424	Devotes to open source FPGA
27	5	0	Unknown	snes_dejitter/425	NES/SNES 240p de-jitter mod
26	8	0	Unknown	myslides/426	Collection of my presentations
26	17	1	Unknown	fifo/427	Generic FIFO implementation with optional FWFT
26	12	0	Unknown	jpegencode/428	JPEG Encoder Verilog
26	2	4	Unknown	quark/429	Stack CPU 🚧 Work In Progress 🚧
26	4	0	Unknown	VirtualTap/430	Mod kit for the Virtual Boy to make it output VGA or RGB video
26	3	0	Unknown	nintendo-switch-i2s-to-spdif/431	I2S to S/PDIF conversion on SiPeed Tang Nano (GOWIN GW1N-LV1) which aims to convert Nintendo Switch's internal I2S signal.
26	15	0	Unknown	sparc64soc/432	OpenSPARC-based SoC
26	5	0	Unknown	HDMI-to-FPGA-to-APA102-Pixels/433	Final Project written in Lucid (verilog) for the Mojo FPGA development board. Reads pixels from HDMI and sends pixel data to 22,000 APA102 LEDs over SPI.
26	16	1	Unknown	Propeller_1_Design/434	Propeller 1 design and example files to be run on FPGA boards.
26	15	0	Unknown	Video-and-Image-Processing-Design-Using-FPGAs/435	Video and Image Processing
26	15	20	Unknown	RetroCade_Synth/436	RetroCade Synth - C64 SID, YM2149, and POKEY audio chips with MIDI interface.
26	3	3	Unknown	time-sleuth/437	Time Sleuth - Open Source Lag Tester
26	8	0	Unknown	core_audio/438	Audio controller (I2S, SPDIF, DAC)
25	6	0	Unknown	fftdemo/439	A demonstration showing how several components can be compsed to build a simulated spectrogram
25	6	0	Unknown	aoOCS/440	The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is not related in any way with Minimig - it is a new and independent Amiga OCS implementation.
25	17	0	Unknown	yafpgatetris/441	Yet Another Tetris on FPGA Implementation
25	14	0	Unknown	dma_axi/442	AXI DMA 32 / 64 bits
25	8	1	Unknown	riscv-soc-cores/443	None
25	26	2	Unknown	block-nvdla-sifive/444	None
25	6	0	Unknown	hackaday_supercon_2019_logic_noise_FPGA_workshop/445	Hackaday Supercon 2019 Logic Noise Badge Workshop
25	16	0	Unknown	TPU-Tensor-Processing-Unit/446	IC implementation of TPU
25	8	0	Unknown	osdvu/447	None
25	9	0	Unknown	book-examples/448	None
25	14	1	Unknown	FAST9-Accelerator/449	FAST-9 Accelerator for Corner Detection
25	13	0	Unknown	peridot/450	'PERIDOT' - Simple & Compact FPGA board
25	5	1	Unknown	Y86-CPU/451	A pipeline CPU in Verilog for the Y86 instruction set.
25	3	0	Unknown	HW-Syn-Lab/452	⚙Hardware Synthesis Laboratory Using Verilog
25	6	0	Unknown	jt49/453	Verilog clone of YM2149
25	13	1	Unknown	ddk-fpga/454	FPGA HDL Sources.
25	12	0	Unknown	chacha/455	Verilog 2001 implementation of the ChaCha stream cipher.
24	10	1	Unknown	ocpi/456	Semi-private RTL development upstream of OpenCPI - this is not the OpenCPI repo!
24	10	0	Unknown	Pong/457	Pong game on an FPGA in Verilog.
24	13	0	Unknown	usb2_dev/458	USB 2.0 Device IP Core
24	5	2	Unknown	ThymesisFlow/459	Memory Disaggregation on POWER9 with OpenCAPI
24	11	3	Unknown	Parser-Verilog/460	A Standalone Structural Verilog Parser
24	20	7	Unknown	MM/461	Miner Manager
24	11	0	Unknown	workshops/462	❄️ 🌟 Workshops with Icestudio and the IceZUM Alhambra board
24	17	0	Unknown	H264/463	H264视频解码verilog实现
24	20	0	Unknown	xge_mac/464	Ethernet 10GE MAC
24	3	0	Unknown	PCI2Nano-PCB/465	An FPGA/PCI Device Reference Platform
24	9	0	Unknown	Uranus/466	Uranus MIPS processor by MaxXing & USTB NSCSCC team
24	10	0	Unknown	verilog-mini-demo/467	Verilog极简教程
23	6	1	Unknown	HPS2FPGAmapping/468	SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
23	14	0	Unknown	vsdmixedsignalflow/469	This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also discusses the steps to modify the current IP layouts inorder to ensure its acceptance by the EDA tools.
23	5	0	Unknown	bapi-rv32i/470	A extremely size-optimized RV32I soft processor for FPGA.
23	6	1	Unknown	cpc_ram_expansion/471	A series of Amstrad CPC PCBs including a backplane, ROM and 512K and 1MByte RAM expansions.
23	12	0	Unknown	SVM-Gaussian-Classification-FPGA/472	SVM Gaussian Classifier of 30x30 greyscale image on Verilog
23	22	1	Unknown	LimeSDR-PCIe_GW/473	Altera Cyclone IV FPGA project for the PCIe LimeSDR board
23	22	0	Unknown	SIMD-architecture/474	Overall multi-core SIMD microarchitecture
23	13	0	Unknown	riscv_soc/475	Basic RISC-V Test SoC
23	11	0	Unknown	Booth_Multipliers/476	Parameterized Booth Multiplier in Verilog 2001
23	13	0	Unknown	ee260_lab/477	EE 260 Winter 2017: Advanced VLSI Design
23	7	1	Unknown	SDR-Micron/478	SDR Micron USB receiver
23	5	0	Unknown	litex_vexriscv_smp/479	Test with LiteX and VexRiscv SMP
23	18	3	Unknown	CAN-Bus-Controller/480	An CAN bus Controller implemented in Verilog
23	15	0	Unknown	Open-CryptoNight-ASIC/481	Open source hardware implementation of classic CryptoNight
23	18	0	Unknown	Open-Source-Network-on-Chip-Router-RTL/482	None
22	11	0	Unknown	verilog-osx/483	Barerbones OSX based Verilog simulation toolchain.
22	4	2	Unknown	OpenSERDES/484	Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
22	2	0	Unknown	literate-broccoli/485	An open source FPGA architecture
22	14	0	Unknown	FFT_Verilog/486	FFT implement by verilog_测试验证已通过
22	3	0	Unknown	thunderclap-fpga-arria10/487	Thunderclap hardware for Intel Arria 10 FPGA
22	17	1	Unknown	Nitro-Parts-lib-SPI/488	Verilog SPI master and slave
22	7	0	Unknown	aemb/489	Multi-threaded 32-bit embedded core family.
22	11	0	Unknown	Icarus_Verilog/490	This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum
22	15	1	Unknown	nysa-verilog/491	Verilog Repository for GIT
22	26	2	Unknown	VexRiscv-verilog/492	Using VexRiscv without installing Scala
22	6	0	Unknown	MIPS-Verilog/493	MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.
22	8	0	Unknown	tinycpu/494	Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes.
22	9	1	Unknown	mipscpu/495	Fully pipelined MIPS CPU in Verilog/SystemVerilog with advanced branch prediction, register renaming, and value prediction
22	2	11	Unknown	circuitgraph/496	Tools for working with circuits as graphs in python
22	6	0	Unknown	picorv32_Xilinx/497	A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
22	3	0	Unknown	EDSAC/498	FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope
22	10	2	Unknown	Zeus/499	NVDLA small config implementation on Zynq ZCU104 (evaluation)
22	7	1	Unknown	VGA1306/500	VGA1306 (VGA-out for DIY Arduboys implemented on an FPGA!)
22	12	0	1 year, 2 months ago	verilog-arbiter/501	A look ahead, round-robing parametrized arbiter written in Verilog.
22	12	0	7 years ago	MIPS-Processor-in-Verilog/502	Processor repo
22	16	1	13 days ago	NandFlashController/503	AXI Interface Nand Flash Controller (Sync mode)
22	6	0	1 year, 1 month ago	iverilog-tutorial/504	Quickstart guide on Icarus Verilog.
22	7	0	8 years ago	usb-de2-fpga/505	Hardware interface for USB controller on DE2 FPGA Platform
22	10	0	6 years ago	CPU/506	Verilog实现的简单五级流水线CPU，开发平台：Nexys3
22	16	1	3 years ago	Design-and-Verification-of-LDPC-Decoder/507	- Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix. - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab.
22	5	0	4 months ago	CPU_start_from_0/508	从零开始设计一个CPU (Verilog)
22	14	1	6 years ago	8051/509	FPGA implementation of the 8051 Microcontroller (Verilog)
22	0	3	23 days ago	MiSTery/510	Atari ST/STe core for MiST
21	4	0	9 years ago	pdfparser/511	None
21	9	1	3 years ago	arty-glitcher/512	FPGA-based glitcher for the Digilent Arty FPGA development board.
21	14	0	2 years ago	Ethernet-design-verilog/513	Gigabit Ethernet UDP communication driver
21	8	0	3 years ago	LeNet_RTL/514	An LeNet RTL implement onto FPGA
21	24	0	28 days ago	risc-v-core/515	This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
21	2	0	1 year, 30 days ago	EI332/516	SJTU EI332 CPU完整实验代码及报告
21	11	1	6 years ago	neural-hardware/517	Verilog library for implementing neural networks.
21	4	1	3 years ago	Verilog-VGA-game/518	A simple game written in Verilog HDL language and display on the VGA screen.
21	8	0	2 months ago	Fixed-Floating-Point-Adder-Multiplier/519	16-bit Adder Multiplier hardware on Digilent Basys 3
21	7	1	6 years ago	azpr_cpu/520	用Altera FPGA芯片自制CPU
21	5	0	7 months ago	wb_intercon/521	Wishbone interconnect utilities
21	2	0	6 months ago	PCI2Nano-RTL/522	An open source FPGA PCI core & 8250-Compatible PCI UART core
21	6	0	21 days ago	xschem_sky130/523	XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
21	7	1	6 years ago	ws2812-verilog/524	This is a Verilog module to interface with WS2812-based LED strips.
21	3	0	15 days ago	core_uriscv/525	Another tiny RISC-V implementation
21	16	2	3 years ago	up5k-demos/526	ice40 UltraPlus demos
21	7	2	2 years ago	buffets/527	Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
21	7	3	1 year, 4 months ago	UPduino-v2.1/528	UPduino
21	4	0	2 years ago	USB/529	FPGA USB 1.1 Low-Speed Implementation
21	4	0	6 months ago	interpolation/530	Digital Interpolation Techniques Applied to Digital Signal Processing
21	8	2	4 months ago	MacPlus_MiSTer/531	Macintosh Plus for MiSTer
21	20	0	8 years ago	RSA4096/532	4096bit RSA project, with verilog code, python test code, etc
21	7	0	5 months ago	srgh-matrix-trinity/533	XBOX 360 advanced glitching - Reverse Engineered using a logic analyzer.
21	7	0	1 year, 11 months ago	PACoGen/534	PACoGen: Posit Arithmetic Core Generator
21	5	1	19 days ago	Bluster/535	CPLD Replacement for A2000 Buster
21	3	1	2 years ago	fpga-virtual-graf/536	None
20	10	2	15 years ago	can/537	CAN Protocol Controller
20	7	0	8 years ago	riscv-invicta/538	A simple RISC-V core, described with Verilog
20	4	2	3 months ago	StereoCensus/539	Verilog Implementation of the Census Transform Stereo Vision algorithm
20	4	2	2 years ago	recon/540	The RECON project creates library for Nios II Microcontroller System and Tool chain. The library includes a collection of hardware configurations and Arduino-style software APIs.
20	10	12	1 year, 1 month ago	nanorv32/541	A small 32-bit implementation of the RISC-V architecture
20	2	0	1 year, 2 months ago	Colorlight-5A-75B/542	Notes for Colorlight-5A-75B.
20	14	0	10 years ago	dma_ahb/543	AHB DMA 32 / 64 bits
20	3	0	2 months ago	difuzz-rtl/544	None
20	11	0	8 years ago	ovs-hw/545	An open source hardware engine for Open vSwitch on FPGA
20	4	0	2 years ago	fpga-examples/546	FPGA examples for 8bitworkshop.com
20	23	3	15 hours ago	ZX-Spectrum_MISTer/547	None
20	2	0	2 years ago	gameduino-fpga-mods/548	Mods of the FPGA code from @jamesbowman's Gameduino file repository
20	4	0	7 months ago	Async-Karin/549	Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.
20	3	0	10 months ago	serv_soc/550	SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
20	2	0	2 years ago	enigmaFPGA/551	Enigma in FPGA
20	5	0	2 years ago	redpid/552	migen + misoc + redpitaya = digital servo
20	7	0	a month ago	Vision-FPGA-SoM/553	tinyVision.ai Vision & Sensor FPGA System on Module
20	19	3	3 years ago	Cosmos-OpenSSD/554	None
20	18	2	9 months ago	blake2/555	Hardware implementation of the blake2 hash function
20	32	0	3 years ago	sata3_host_controller/556	It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
20	5	0	3 months ago	ctfs/557	ctfs write-up
20	1	0	1 year, 8 months ago	BusPirateUltraHDL/558	Verilog for the Bus Pirate Ultra FPGA
20	6	0	1 year, 3 months ago	Computer-Experiment-on-the-principle-of-computer-composition/559	杭电计算机学院-《计算机组成原理》上机实验代码工程文件
20	17	10	1 year, 2 months ago	UHD-Fairwaves/560	Fairwaves version of the UHD drivers, tweaked to support Fairwaves UmTRX.
20	6	0	4 years ago	Yoshis-Nightmare/561	FPGA Based Platformer Video Game
20	13	1	1 year, 6 months ago	matrix-creator-fpga/562	Reference HDL code for the MATRIX Creator's Spartan 6 FPGA
20	14	0	1 year, 2 months ago	x393_sata/563	mirror of https://git.elphel.com/Elphel/x393_sata
20	6	0	9 days ago	jelly/564	Original FPGA platform
20	13	1	1 year, 3 months ago	Pepino/565	None
20	12	0	4 years ago	4-way-set-associative-cache-verilog/566	Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
20	5	0	3 months ago	Pet2001_Nexys3/567	A Commodore PET in an FPGA.
20	1	0	6 months ago	MIPS54SP-Lifesaver/568	None
20	4	0	a month ago	notary/569	Notary: A Device for Secure Transaction Approval 📟
19	6	1	3 years ago	UPDuino-OV7670-Camera/570	Design to connect Lattice Ultraplus FPGA to OV7670 Camera Module
19	16	0	a month ago	sha512/571	Verilog implementation of the SHA-512 hash function.
19	6	0	1 year, 2 months ago	core_soc/572	Basic Peripheral SoC (SPI, GPIO, Timer, UART)
19	14	1	8 years ago	turbo8051/573	turbo 8051
19	9	0	5 years ago	Make-FPGA/574	Repository of Verilog code for Make:FPGA book Chapters 2 & 3.
19	14	0	2 years ago	face_detect_open/575	A Voila-Jones face detector hardware implementation
19	5	9	9 years ago	hdl_devel/576	A new CASPER toolflow based on an HDL primitives library
19	7	0	24 days ago	fpga-bpf/577	A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark
19	9	0	1 year, 2 months ago	00_Image_Rotate/578	视频旋转（2019FPGA大赛）
19	7	1	8 years ago	fpgaminer-vanitygen/579	Open Source Bitcoin Vanity Address Generation on FPGAs
19	2	0	2 years ago	verifla/580	Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm
19	8	0	5 years ago	CoCo3FPGA/581	FPGA implementation of the TRS-80 Color Computer 3 in Verilog, by Gary Becker et al.
19	20	0	8 months ago	vsdstdcelldesign/582	This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.
19	9	0	a month ago	uart/583	A simple implementation of a UART modem in Verilog.
19	11	0	1 year, 2 months ago	DA_PUF_Library/584	Defense/Attack PUF Library (DA PUF Library)
19	0	0	1 year, 9 months ago	risc-v/585	RISC-VのCPU作った
19	4	0	4 years ago	MesaBusProtocol/586	Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces
19	11	0	2 years ago	trainwreck/587	Original RISC-V 1.0 implementation. Not supported.
19	6	0	1 year, 8 months ago	tinyfpga_examples/588	Verilog example programs for TinyFPGA
19	9	0	8 months ago	INSIDER-System/589	An FPGA-based full-stack in-storage computing system.
19	0	3	2 years ago	HDL-deflate/590	FPGA implementation of deflate (de)compress RFC 1950/1951
19	2	1	5 years ago	icestick-vga-test/591	Test of ICEstick PLL usage with Yosys/Arachne-PNR/Icetools
19	8	3	2 years ago	s7_mini_fpga/592	Example designs for the Spartan7 "S7 Mini" FPGA board
19	2	0	6 years ago	BCOpenMIPS/593	跟着《自己动手写 CPU》书上写的 OpenMIPS CPU。
19	8	0	4 years ago	Centaur/594	Centaur, a framework for hybrid CPU-FPGA databases
19	5	0	1 year, 3 months ago	bitcoin_mining/595	Simple test fpga bitcoin miner
19	11	0	5 years ago	ethernet_10ge_mac_SV_tb/596	SystemVerilog testbench for an Ethernet 10GE MAC core
19	2	0	7 months ago	caravel_fpga250/597	FPGA250 aboard the eFabless Caravel
19	1	0	3 years ago	UART2NAND/598	Interface for exposing raw NAND i/o over UART to enable pc-side modification.
19	13	0	1 year, 8 months ago	RISC-V-32I/599	体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
19	6	0	2 years ago	arm_vhdl/600	Portable FPGA project based on the ARM DesignStart bundle with ARM Cortex-M3 processor
19	5	2	2 months ago	mipi-demo/601	MIPI CSI-2 + MIPI CCS Demo
19	12	0	3 months ago	evoapproxlib/602	Library of approximate arithmetic circuits
19	2	0	4 years ago	RiverRaidFPGA/603	River Raid game on FPGA
19	14	1	1 year, 10 months ago	gemac/604	Gigabit MAC + UDP/TCP/IP offload Engine
18	4	0	9 years ago	verilog-vga-controller/605	A very simple VGA controller written in verilog
18	4	0	3 months ago	k1801/606	1801 series ULA reverse engineering
18	3	4	2 years ago	fLaCPGA/607	Implementation of fLaC encoder/decoder for FPGA
18	1	0	3 months ago	biggateboy/608	WIP Big FPGA Gameboy
18	7	0	1 year, 4 months ago	DSP-RTL-Lib/609	RTL Verilog library for various DSP modules
18	1	0	3 years ago	VerilogCommon/610	A repo of basic Verilog/SystemVerilog modules useful in other circuits.
18	7	0	3 years ago	Verilog_Calculator_Matrix_Multiplication/611	This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
18	0	0	3 years ago	sdaccel_chisel_integration/612	Chisel Project for Integrating RTL code into SDAccel
18	2	0	1 year, 4 months ago	dbgbus/613	A collection of debugging busses developed and presented at zipcpu.com
18	1	0	19 days ago	SmolDVI/614	Low-area DVI experiment for iCE40 UP5k and HX1k FPGAs
18	1	0	2 years ago	spi_tb/615	CPOL=0, CPHA=0 SPI core for practicing formal verification with yosys
18	5	1	3 years ago	anlogic-picorv32/616	Optimized picorv32 core for anlogic FPGA
18	4	0	1 year, 3 months ago	CNNAF-CNN-Accelerator/617	CNN-Accelerator based on FPGA developed by verilog HDL.
18	1	0	a month ago	no2muacm/618	Drop In USB CDC ACM core for iCE40 FPGA
18	8	0	1 year, 1 month ago	usb2sniffer/619	USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)
18	17	1	9 years ago	MIPS-in-Verilog/620	An implementation of MIPS single cycle datapath in Verilog.
18	0	0	1 year, 3 months ago	Life_MiSTer/621	Conway's Game of Life in FPGA
18	15	0	6 months ago	DSX_KCXG/622	个人资料，合肥工业大学宣城校区2019年-2020年第二学期（大三下学期），与物联网工程专业的课程有关资料，含课件、实验报告、课设报告等
18	7	0	10 years ago	video_stream_scaler/623	Video Stream Scaler
18	5	0	1 year, 7 months ago	Digital_Front_End_Verilog/624	None
18	71	17	a day ago	caravel_user_project/625	https://caravel-user-project.readthedocs.io
18	6	0	2 years ago	tinyfpga-bx-game-soc/626	A PicoRV32 SoC for the TinyFPGA BX with peripherals designed for building games
18	4	0	1 year, 1 month ago	USTC-ComputerArchitecture-2020S/627	Code for "Computer Architecture" in 2020 Spring.
17	1	0	3 years ago	fpga-sram/628	mystorm sram test
17	0	0	4 months ago	my_hdmi_device/629	New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!
17	5	1	5 years ago	mips/630	Mips处理器仿真设计
17	9	8	4 years ago	pars/631	None
17	4	1	4 years ago	handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/632	None
17	10	2	11 months ago	KWS-SoC/633	This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.
17	1	0	2 months ago	jtopl/634	Verilog module compatible with Yamaha OPL chips
17	0	0	7 months ago	ucisc/635	None
17	4	0	1 year, 8 months ago	RePLIA/636	FPGA Based lock in amplifier
17	13	0	4 years ago	FreeAHB/637	AHB Master
17	5	0	6 years ago	orgexp/638	Computer Organization Experiment, Shi Qingsong, Zhejiang University.
17	4	2	5 years ago	icestickPWM/639	Simple USB to PWM Peripheral using Lattice iCEStick (Hackaday demo)
17	11	0	8 months ago	verilog-starter-tutorials/640	Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
17	12	0	3 years ago	NoC-Verilog/641	A verilog implementation for Network-on-Chip
17	1	0	3 years ago	8bit-computer/642	Simple 8-bit computer build in Verilog
17	6	0	2 years ago	OV7670_NEXYS4_Verilog/643	This code is used to connect the OV7670 Camera to a NEXYS4 and then display the image on a monitor in Verilog
17	10	0	4 months ago	DDLM/644	Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
17	15	1	1 year, 11 months ago	FPGA_CryptoNight_V7/645	FPGA CryptoNight V7 Minner
17	1	0	7 months ago	ics-adpcm/646	Programmable multichannel ADPCM decoder for FPGA
17	6	0	2 months ago	core_usb_cdc/647	Basic USB-CDC device core (Verilog)
17	6	0	5 years ago	nes_mappers/648	NES mappers
17	3	2	3 months ago	OpenIRV/649	Open-source thermal camera project
17	7	0	Unknown	nica/650	An infrastructure for inline acceleration of network applications
17	6	0	4 years ago	computer-systems-ucas/651	中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
17	2	0	5 years ago	QuickSilverNEO/652	None
17	10	0	5 years ago	heterosim/653	HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design space exploration is enabled by a wide range of system configurations. A complete simulation flow with compiler support is provided so that a full system simulation can be performed with various performance metrics returned.
17	18	1	17 days ago	apio-examples/654	🌱 Apio examples
17	3	0	9 months ago	3DORGB/655	RGB Project for most 3DO consoles.
17	9	0	Unknown	Convolution-using-systolic-arrays/656	None
17	5	0	7 years ago	FPGA_Stereo_Depth_Map/657	None
17	17	2	a day ago	oscpu-framework/658	A Verilator-based demo.
17	4	0	9 years ago	amber_samples/659	None
17	9	0	3 years ago	posture_recognition_CNN/660	To help machines learn what we human beings are doing via a camera is important. Once it comes true, machines can make different responses to all kinds of human's postures. But the process is very difficult as well, because usually it is very slow and power-consuming, and requires a very large memory space. Here we focus on real-time posture recognition, and try to make the machine "know" what posture we make. The posture recognition system is consisted of DE10-Nano SoC FPGA Kit, a camera, and an HDMI monitor. SoC FPGA captures video streams from the camera, recognizes human postures with a CNN model, and finally shows the original video and classification result (standing, walking, waving, etc.) via HDMI interface.
17	6	2	4 months ago	Simulator_CPU/661	Pipeline CPU of MIPS architecture with L1 Data Cache by Verilog
17	2	1	Unknown	raiden/662	Raiden project
17	6	1	Unknown	OpenPhySyn/663	EDA physical synthesis optimization kit
17	3	30	Unknown	TART/664	Transient Array Radio Telescope
17	10	0	Unknown	Reindeer_Step/665	Reindeer Soft CPU for Step CYC10 FPGA board
17	6	0	Unknown	fpga-ml-accelerator/666	This repository hosts the code for an FPGA based accelerator for convolutional neural networks
17	4	7	5 years ago	vector06cc/667	Вектор-06ц в ПЛИС / Vector-06c in FPGA
17	10	0	Unknown	2-way-Set-Associative-Cache-Controller/668	Synthesizable and Parameterized Cache Controller in Verilog
17	2	0	Unknown	ws2812-core/669	verilog core for ws2812 leds
17	11	0	Unknown	FPGA-SM3-HASH/670	Description of Chinese SM3 Hash algorithm with Verilog HDL
17	2	0	Unknown	Hardware-Accelerated-SNN/671	Architecture for Spiking Neural Network
16	2	0	Unknown	PitchShifter/672	Change the pitch of your voice in real-time!
16	7	1	Unknown	tonic/673	A Programmable Hardware Architecture for Network Transport Logic
16	1	0	Unknown	Home-Brew-Computer/674	SystemOT, yet another home brew cpu.
16	7	0	Unknown	steel-core/675	Steel is a RISC-V processor core that implements the RV32I and Zicsr instruction sets of the RISC-V specifications.
16	11	0	Unknown	matrix-voice-fpga/676	HDL code for the MATRIX Voice's Spartan 6 FPGA http://voice.matrix.one
16	5	0	Unknown	fpga_image_processing/677	IP operations in verilog (simulation and implementation on ice40)
16	0	0	Unknown	mera400f/678	MERA-400 in an FPGA
16	7	0	Unknown	PCIE_AXI_BRIDGE/679	Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
16	9	2	Unknown	MemTest_MiSTer/680	None
16	5	0	Unknown	cpus-pdp8/681	FPGA based PDP-8/i clone in verilog. Includes several TSS/8 sources and utiltities to build from source
16	10	0	Unknown	Hardware_circular_buffer_controller/682	This is a circular buffer controller used in FPGA.
16	4	0	Unknown	opengg/683	OpenGL-like graphics pipeline on a Xilinx FPGA
16	5	0	Unknown	no2bootloader/684	USB DFU bootloader gateware / firmware for FPGAs
16	8	0	Unknown	JPEG-Decoder/685	Verilog Code for a JPEG Decoder
16	6	1	Unknown	iir-bandstop-filter/686	Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic
16	10	2	Unknown	freepdk-45nm/687	ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
16	6	0	Unknown	icestick/688	Simple demo for Lattice iCEstick board as seen on Hackaday
16	7	5	Unknown	polaris/689	RISC-V RV64IS-compatible processor for the Kestrel-3
16	22	1	Unknown	moneroasic/690	Cryptonight Monero Verilog code for ASIC
16	2	0	Unknown	WitnessProtection/691	in FPGA
16	6	0	Unknown	fpga-gpu/692	A basic GPU for altera FPGAs
16	2	0	Unknown	enxor-logic-analyzer/693	FPGA Logic Analyzer and GUI
16	14	0	Unknown	logi-pong-chu-examples/694	example code for the logi-boards from pong chu HDL book
16	12	13	Unknown	sancus-core/695	Minimal OpenMSP430 hardware extensions for isolation and attestation
16	10	1	Unknown	AHB_Bus_Matrix/696	None
16	3	2	Unknown	SoC_Automation/697	SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.
16	6	0	Unknown	MIDI-Stepper-Synth-V2/698	Virginia Tech AMP Lab Version of the MIDI Stepper Synth. Uses FPGA and 32 Stepper Motors.
16	2	0	Unknown	de10-nano-riscv/699	A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano
16	14	1	Unknown	fpga-nn/700	NN on FPGA
16	0	0	1 year, 27 days ago	ulx3s_examples/701	Example Verilog code for Ulx3s
16	10	0	2 months ago	vivado-ip-cores/702	IP Cores that can be used within Vivado
16	16	0	4 months ago	computer-organization-lab/703	中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU
16	14	0	2 years ago	gameduino/704	My own version of the @JamesBowman's Gameduino file repository
16	0	0	6 months ago	Hardware_Design/705	None
16	6	0	3 years ago	Autonomous-Drone-Design/706	Design real-time image processing, object recognition and PID control for Autonomous Drone.
16	6	1	1 year, 8 months ago	ZBC---The-Zero-Board-Computer/707	Based heavily on zet.aluzina.org and Terasic DE0
16	4	0	7 years ago	magukara/708	FPGA-based open-source network tester
16	15	0	3 years ago	FPGA_SM4/709	FPGA implementation of Chinese SM4 encryption algorithm.
16	4	1	23 days ago	saxonsoc-ulx3s-bin/710	The binaries for SaxonSoc Linux and other configurations
16	11	0	4 years ago	polyphase_filter_prj/711	软件无线电课设：多相滤波器的原理、实现及其应用，从采样率变换、多相滤波器结构到信道化收发机应用都有matlab介绍和FPGA仿真结果，含答辩PPT、学习笔记和个人总结。
16	4	0	19 days ago	mpsoc_example/712	None
16	13	1	4 years ago	lisnoc/713	LIS Network-on-Chip Implementation
16	3	5	1 year, 1 month ago	MiSTer-Arcade-SEGASYS1/714	FPGA implementation of SEGA SYSTEM 1 arcade board
16	1	0	1 year, 29 days ago	mips-cpu/715	💻 A 5-stage pipeline MIPS CPU implementation in Verilog.
16	2	0	a month ago	openlogicbit/716	Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
16	9	0	4 years ago	Curso-Electronica-Digital-para-makers-con-FPGAs-Libres/717	Curso de 35h sobre el diseño de sistemas digitales usando FPGAs libres, orientado para makers
16	5	0	9 years ago	openmsp430/718	openMSP430 CPU core (from OpenCores)
16	3	0	5 years ago	verilog_tutorials_BB/719	verilog tutorials for iCE40HX8K Breakout Board
16	1	0	2 years ago	Merlin/720	RISC-V RV32I[C] CPU (Apache-2.0) - Merlin
15	1	0	10 years ago	Oberwolfach-explorations/721	collaboration on work in progress
15	0	0	1 year, 8 months ago	FPGAGameBoy/722	an implementation of the GameBoy in Verilog
15	1	0	3 years ago	UPduino-Mecrisp-Ice-15kB/723	Mecrisp-Ice Forth running on 16bit j1a processor (iCE40UP5k based UPduino board) with full 15kB of bram and 48bit Floating Point Library.
15	0	1	2 months ago	Deep-DarkFantasy/724	Global Dark Mode for ALL apps on ANY platforms.
15	10	1	2 years ago	zuma-fpga/725	Fine Grain FPGA Overlay Architecture and Tools
15	3	1	4 years ago	Menu_MIST/726	Dummy FPGA core to display menu at startup
15	16	21	13 hours ago	yosys-symbiflow-plugins/727	Plugins for Yosys developed as part of the SymbiFlow project.
15	5	2	6 years ago	Modular-Exponentiation/728	Verilog Implementation of modular exponentiation using Montgomery multiplication
15	8	0	12 years ago	verilog_cordic_core/729	configurable cordic core in verilog
15	12	1	3 years ago	Viterbi-Decoder-in-Verilog/730	An efficient implementation of the Viterbi decoding algorithm in Verilog
15	5	1	a month ago	CPU/731	None
15	5	4	6 days ago	VossII/732	The source code to the Voss II Hardware Verification Suite
15	4	1	4 years ago	fpga-wpa-psk-bruteforcer/733	WPA-PSK cracking for FPGA devices
15	8	0	3 years ago	FFTVisualizer/734	This project demonstrates DSP capabilities of Terasic DE2-115
15	6	4	1 year, 10 months ago	yosys-bench/735	Benchmarks for Yosys development
15	5	0	2 years ago	Flappy-Bird/736	FPGA program :VGA-GAME
15	7	0	2 years ago	Computer-Organization-and-Architecture-LAB/737	Solution to COA LAB Assgn, IIT Kharagpur
15	1	0	5 months ago	verilog/738	None
15	0	0	1 year, 8 months ago	wbfmtx/739	A wishbone controlled FM transmitter hack
15	10	0	2 years ago	Verilog-FIR/740	FIR implemention with Verilog
15	3	0	2 months ago	icozip/741	A ZipCPU demonstration port for the icoboard
15	14	1	11 years ago	dvb_s2_ldpc_decoder/742	DVB-S2 LDPC Decoder
15	5	1	1 year, 8 months ago	RISC-V-CPU/743	A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
15	2	0	4 years ago	NeuralHDL/744	None
15	7	0	1 year, 4 months ago	verilog/745	None
15	6	1	5 years ago	dnn-sim/746	None
15	11	0	2 years ago	32-bit-MIPS-Processor/747	A 32-bit MIPS processor used Altera Quartus II with Verilog.
15	3	1	7 years ago	descrypt-ztex-bruteforcer/748	descrypt-ztex-bruteforcer
15	1	0	3 years ago	iCEstick-hacks/749	iCEstick iCE40-HX1K FPGA hacks ~ iCEfm FM Transmitter
15	10	1	6 years ago	i2s/750	i2s core, with support for both transmit and receive
15	3	0	4 years ago	OpenMIPS/751	OpenMIPS——《自己动手写CPU》处理器部分
15	9	0	4 years ago	AXI_BFM/752	AXI4 BFM in Verilog
15	3	1	1 year, 10 months ago	net2axis/753	Verilog network module. Models network traffic from pcap to AXI-Stream
15	9	0	2 years ago	RISC-Processor/754	32-bit RISC processor
15	9	0	6 years ago	NetFPGA-10G-UPB-OpenFlow/755	An OpenFlow implementation for the NetFPGA-10G card
15	6	0	1 year, 8 months ago	digital_lab/756	Laboratory works for digital electronics course in Kyiv Polytechnic Institute, Department of Design of Electronic Digital Equipment, Electronics faculty
15	3	0	5 months ago	hello-verilog/757	Hello Verilog by Mac + VSCode
15	9	0	3 years ago	SHA256Hasher/758	SHA-256 IP core for ZedBoard (Zynq SoC)
15	4	0	2 months ago	arrowzip/759	A ZipCPU based demonstration of the MAX1000 FPGA board
15	3	0	4 years ago	fpga-synth/760	FPGA based modular synth.
15	5	0	6 years ago	fpga-spartan6/761	Support for zScale on Spartan6 FPGAs
14	2	1	1 year, 9 months ago	galaksija/762	Galaksija computer for FPGA
14	2	1	3 years ago	mikrobus-upduino/763	Dual MikroBUS board for Upduino 2 FPGA
14	22	2	3 years ago	FPGA-Keccak-Miner/764	None
14	5	1	1 year, 6 months ago	max2-audio-dac/765	24-bit Stereo Audio DAC for Raspberry Pi
14	13	0	2 months ago	fpga-sdk-prj/766	FPGA-based SDK projects for SCRx cores
14	3	0	3 months ago	SpGEMM/767	None
14	5	1	2 years ago	ComputerArchitectureLab/768	This repository is used to release the Labs of Computer Architecture Course from USTC
14	0	0	3 years ago	iPxs-Text/769	Text for a iPxs-Collection.
14	9	0	5 months ago	FPGA_DevKit_HX1006A/770	None
14	2	0	4 months ago	bitmips2019/771	None
14	9	7	10 days ago	Archie_MiSTer/772	Acorn Archimedes for MiSTer
14	4	0	1 year, 5 months ago	Jaguar_MiSTer_new/773	None
14	4	0	5 years ago	ASIC-FPGA-tetris/774	a FPGA implementation for tetris game.
14	2	0	1 year, 10 months ago	systolic-array-matrix-multiplier/775	A systolic array matrix multiplier
14	14	1	8 years ago	ASIC/776	EE 287 2012 Fall
14	4	0	6 years ago	Computer-Architecture/777	A pipelined MIPS CPU supporting 31 MIPS instructions, interrupt and cache.
14	2	1	2 years ago	Conways-Game-of-Life-with-Vlang/778	Conway's life game in V
14	8	0	4 years ago	ring_network-based-multicore-/779	多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency
14	3	0	2 years ago	Ada-PicoRV32-example/780	Example of Ada code running on the PicoRV32 RISC-V CPU for FPGA
14	2	0	2 years ago	pinky8bitcpu/781	Pinky (8-bit CPU) written in Verilog and an Assembler written in Python 3
14	1	1	an hour ago	chad/782	A self-hosting Forth for J1-style CPUs
14	7	0	3 years ago	pciebench-netfpga/783	pcie-bench code for NetFPGA/VCU709 cards
14	13	1	2 years ago	OpenHPSDR-Firmware/784	This is the verilog code for the various FPGA in the OpenHPSDR Radios
14	3	0	5 years ago	FPGA/785	computer hardware system including ps2/vga with tank war game in verilog and mips
14	10	0	2 years ago	AD9361_TX_MSK/786	A project demonstrate how to config ad9361 to TX mode and how to transmit MSK
14	5	0	2 months ago	ps-fpga/787	The PS-FPGA project (top level)
14	10	4	5 months ago	Arcade-GnG_MiSTer/788	Arcade Ghosts'n Goblins for MiSTer
14	7	0	3 months ago	Atari7800_MiSTer/789	Atari 7800 for MiSTer
14	4	7	3 years ago	liquid-router/790	The Subutai™ Router open hardware project sources.
14	2	4	1 year, 5 months ago	fluent10g/791	Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet
14	2	0	1 year, 3 months ago	Nu6509/792	Emulate a 6509 with a 6502
14	10	1	5 years ago	BD3_FPGA/793	新一代北斗卫星导航监测接收机的FPGA实现
14	6	2	5 years ago	idea/794	iDEA FPGA Soft Processor
14	7	0	17 years ago	jtag/795	JTAG Test Access Port (TAP)
14	4	0	1 year, 11 months ago	cdsAsync/796	cdsAsync: An Asynchronous VLSI Toolset & Schematic Library
14	13	1	2 years ago	FPGA_rtime_HDR_video/797	We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.
14	4	0	6 days ago	FPGA_Book_Experiments/798	My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
14	7	0	2 years ago	vp_awsfpga/799	Virtual Platform for AWS FPGA support
14	4	0	3 years ago	crap-o-scope/800	crap-o-scope scope implementation for icestick
14	2	1	1 year, 7 months ago	SNKVerilog/801	Verilog definitions of custom SNK chips, for repairs and preservation.
14	13	1	3 years ago	c64-dodgypla/802	Commodore 64 PLA replacement
14	4	0	1 year, 11 months ago	yoloRISC/803	A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
14	0	0	3 years ago	RISCV-CPU/804	SJTU Computer Architecture(1) Hw
14	6	0	2 years ago	Nexys-4-DDR-Ethernet-Mac/805	Ethernet MAC for the Digilent Nexys 4 DDR FPGA.
14	4	0	14 days ago	OPDB/806	OpenPiton Design Benchmark
14	2	0	1 year, 7 months ago	ice40_8bitworkshop/807	"Designing Video Game Hardware in Verilog" in iCE40HX8K Breakout Board.
14	6	0	1 year, 1 month ago	Azure-SDR/808	SW SDR
14	1	1	10 months ago	INT_FP_MAC/809	INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
14	10	0	3 years ago	FPGA-Mnist/810	Hand written number classification done in hardware (De1-SoC board) using neural networks
14	1	0	3 months ago	arty-videocap/811	Repeat and capture the video signal with Digilent Arty-A7 and a video extender board.
14	10	0	Unknown	sha3/812	FIPS 202 compliant SHA-3 core in Verilog
14	12	0	3 years ago	riscvv/813	an open source uvm verification platform for e200 (riscv)
14	4	0	Unknown	riscv_sbc/814	A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
14	2	1	7 years ago	ethpipe/815	EtherPIPE: an Ethernet character device for packet processing
14	3	0	7 months ago	NeoChips/816	Replacement "chips" for NeoGeo systems
14	7	0	1 year, 11 months ago	Delta-sigma-ADC-verilog/817	Delta-sigma ADC,PDM audio FPGA Implementation
14	3	0	4 months ago	riscv-core/818	A customized RISCV core made using verilog
13	4	0	7 years ago	80211scrambler/819	Tools for working with the 802.11B scrambler when writing Packet-in-Packet exploits.
13	11	0	2 years ago	wb_sdram_ctrl/820	SDRAM controller with multiple wishbone slave ports
13	0	1	11 months ago	TurboMaster/821	Reverse Engineering of the Schnedler Systems 4MHz TurboMaster accelerator cartridge for the Commodore 64
13	4	0	25 days ago	fpga/822	Various FPGA projects for the TinyFPGA BX, Numato Lab Mimas V2, iCESugar v1.5, iCESugar Nano and Colorlight 5A-75B.
13	12	4	4 years ago	DE1-SoC-Sound/823	None
13	4	0	Unknown	ShootingGame-FPGA/824	Using verilog-HDL, xilinx-ISE and nexys-iii. A shooting game based on VGA and ps/2 keyboard.
13	0	0	Unknown	fpga_tv/825	Some crazy experiments about using a FPGA to transmit a TV signal old-style
13	2	0	Unknown	parallel-processor-design/826	Super scalar Processor design
13	6	1	1 year, 3 months ago	Low-Cost-and-Programmable-CRC/827	Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
13	4	1	Unknown	dyract/828	DyRACT Open Source Repository
13	6	0	4 years ago	Rocket-Chip/829	None
13	10	2	3 years ago	HLS_Legup/830	None
13	13	0	3 years ago	single-cycle-CPU/831	单周期CPU设计与实现
13	6	0	6 years ago	mips32r1_core/832	A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.
13	8	0	5 years ago	verilog-tetris/833	A Verilog implementation of the popular video game Tetris.
13	3	2	Unknown	hardcaml-riscv/834	RISC-V instruction set CPUs in HardCaml
13	4	1	Unknown	subservient/835	Small SERV-based SoC primarily for OpenMPW tapeout
13	12	0	1 year, 10 months ago	Pmod-I2S2/836	None
13	5	7	a month ago	shapool-core/837	FPGA core for SHA256d mining targeting Lattice iCE40 devices.
13	8	0	3 years ago	TinyFPGA-SoC/838	Opensource building blocks for TinyFPGA microcontrollers and retro computers.
13	11	0	8 years ago	4way-cache/839	Verilog cache implementation of 4-way FIFO 16k Cache
13	4	0	2 years ago	xulalx25soc/840	A System on a Chip Implementation for the XuLA2-LX25 board
13	4	0	8 years ago	mcs-4/841	4004 CPU and MCS-4 family chips
13	2	0	Unknown	CNN-Based-FPGA/842	CNN implementation based FPGA
13	5	0	Unknown	openzcore/843	powerpc processor prototype and an example of semiconductor startup biz plan
13	9	1	Unknown	mips_16/844	Educational 16-bit MIPS Processor
13	11	1	4 years ago	Radix-2-FFT/845	Verilog code for a circuit implementation of Radix-2 FFT
13	10	0	2 years ago	verilog-divider/846	a super-simple pipelined verilog divider. flexible to define stages
13	3	2	Unknown	gateware/847	IP submodules, formatted for easier CI integration
13	1	3	Unknown	oram/848	Hardware implementation of ORAM
13	12	1	2 years ago	digital-design-lab-manual/849	Digital Design Labs
13	4	0	Unknown	ssith-aws-fpga/850	Host software for running SSITH processors on AWS F1 FPGAs
13	8	0	4 months ago	32-Verilog-Mini-Projects/851	Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
13	1	0	2 months ago	xyloni/852	This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.
13	2	1	Unknown	soc-lm32/853	Open source/hardware SoC plattform based on the lattice mico 32 softcore
13	7	0	4 months ago	64-bit-Universal-Floating-Point-ISA-Compute-Engine/854	RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
13	4	7	9 months ago	scarv-cpu/855	SCARV: a side-channel hardened RISC-V platform
13	1	0	6 years ago	VerilogCogs/856	Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.
13	14	4	4 years ago	test_jpeg/857	This is a myhdl test environment for the open-cores jpeg_encoder.
13	9	0	5 years ago	Verilog-Single-Cycle-Processor/858	Verilog
13	0	0	4 years ago	fpga_csgo/859	Counter Strike: Global Offensive FPGA Version (LOL)
13	1	0	1 year, 10 days ago	RISC-V/860	A simple RISC-V CPU written in Verilog.
13	6	0	8 days ago	M65C02A/861	Enhanced 6502/65C02 Microprogrammed FPGA Processor Core (Verilog-2001)
13	11	5	5 months ago	rp_lock-in_pid/862	Lock-in and PID application for RedPitaya enviroment
13	2	0	1 year, 6 months ago	color3/863	Information about eeColor Color3 HDMI FPGA board
13	3	1	1 year, 10 months ago	TMR/864	Triple Modular Redundancy
13	0	0	1 year, 24 days ago	fomu-vga/865	None
13	3	0	a month ago	core_dbg_bridge/866	UART -> AXI Bridge
13	4	0	11 months ago	SortingNetwork/867	Implement a bitonic sorting network on FPGA
13	8	0	4 years ago	ice40-stm32-sdram/868	Test code to talk from STM32 MCU over FSMC to SDRAM on ICE40 FPGA
13	5	4	2 days ago	jtdd/869	Double Dragon FPGA core
13	4	0	2 years ago	MIPS-Architecture-CPU-design/870	BUAA SCSE - Computer Organization - Pipeline CPU design
13	8	2	9 months ago	elec50010-2020-verilog-lab/871	Verilog lab material for ELEC50010 class
13	6	2	6 years ago	Pano-Logic-Zero-Client-G2-FPGA-Demo/872	Constraints file and Verilog demo code for the Pano Logic Zero Client G2
13	2	2	1 year, 9 months ago	upduino/873	None
13	6	0	2 years ago	up5k_vga/874	A complete 65C02 computer with VGA output on a Lattice Ultra Plus FPGA
13	9	0	2 years ago	fpga-tutorial/875	FPGA tutorial
12	11	0	9 years ago	wimax_ofdm/876	Partial Verilog implimentation of a WiMAX OFDM Phy
12	3	0	3 years ago	ipxactexamplelib/877	Contains examples to start with Kactus2.
12	0	0	1 year, 6 months ago	eecs151/878	http://inst.eecs.berkeley.edu/~eecs151/fa19/
12	11	0	5 years ago	Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM/879	Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)
12	7	0	1 year, 11 months ago	verilog-doc/880	All About HDL
12	15	0	3 days ago	greta-oto/881	An open source GNSS receiver
12	2	0	2 years ago	cpld-6502/882	6502 CPU in 4 small CPLDs
12	3	0	3 years ago	bladerf-dvbs2/883	16-APSK DVB-S2 Transmitter for BladeRF
12	4	1	5 months ago	rodinia/884	AGM bitstream utilities and decoded files from Supra
12	3	0	2 years ago	fpga_1943/885	Verilog re-implementation of the famous CAPCOM arcade game
12	8	0	3 years ago	fpga-hdl/886	A set of small Verilog projects, to simulate and implement on FPGA development boards
12	7	0	3 years ago	CPU/887	CS3339 Computer Architecture class project - 5 stage MIPS-like processor with forwarding, hazard control, no exception handling.
12	5	0	5 months ago	DVP_to_UDP/888	Uncompressed video uver UDP using 1000BASE-T Ethernet on Cyclone IV FPGA
12	13	0	5 years ago	Asynchronous-FIFO/889	Asynchronous fifo in verilog
12	1	0	7 years ago	milkymist-mmu/890	Milkymist MMU project
12	3	0	3 years ago	bextdep/891	Reference Hardware Implementations of Bit Extract/Deposit Instructions
12	5	0	2 years ago	BareBonesCortexM0/892	Extremely basic CortexM0 SoC based on ARM DesignStart Eval
12	1	0	18 hours ago	BubbleDrive8/893	Konami Bubble System Bubble Memory Cartridge FBM-#101 Emulator
12	3	0	6 months ago	Nexys-4-DDR-Keyboard/894	None
12	5	0	4 years ago	riffa2/895	Full duplex version of KastnerRG/riffa#30
12	1	0	8 months ago	Verilog-Playground/896	Verilog Experiment Area
12	2	0	9 years ago	bfcpu2/897	A pipelined brainfuck softcore in Verilog
12	5	0	1 year, 2 months ago	aes/898	Advanced encryption standard implementation in verilog.
12	4	1	5 years ago	ICEd/899	Open Hardware for Open Source FPGA Toolchain
12	0	0	5 years ago	yosys-ice-experiments/900	Experiments for iCEstick evaluation board with iCE40HX-1k FPGA - using open source toolchain
12	4	0	2 years ago	digital-design/901	An introduction to integrated circuit design with Verilog and the Papilio Pro development board.
12	7	7	5 years ago	pifo-hardware/902	None
12	7	0	2 years ago	Zynq-7000-DPU-TRD/903	Zynq-7000 DPU TRD
12	5	0	a month ago	core_usb_bridge/904	USB -> AXI Debug Bridge
12	6	0	5 years ago	gng/905	Gaussian noise generator Verilog IP core
12	4	0	9 years ago	oc-i2c/906	I2C controller core from Opencores.org
12	4	0	7 months ago	Image-Classification-using-CNN-on-FPGA/907	Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
12	4	0	6 years ago	radio-86rk-wxeda/908	Port of the original radio-86rk_SDRAM Altera DE1 code to the WXEDA board
12	2	0	5 years ago	consolite-hardware/909	A hardware implementation of the Consolite game console written in Verilog.
12	2	4	2 years ago	pumpkin/910	None
12	0	0	2 years ago	ulx3s-foss-blinky/911	A template project for the ULX3S ECP5 FPGA board using only Open Source Software
12	9	5	5 months ago	Amstrad_MiSTer/912	Amstrad CPC 6128 for MiSTer
12	1	1	2 years ago	Electronic-competition/913	全国大学生电子设计大赛往年赛题--仪器仪表类练习
12	11	0	2 years ago	CurriculumDesign-PrinciplesOfComputerOrganization/914	华中科技大学计算机15级计算机组成原理课程设计，分别用logisim和Verilog实现简单CPU
12	9	1	4 years ago	PUF-lab/915	FPGA implementation of a physical unclonable function for authentication
12	0	0	1 year, 5 months ago	zevios/916	original 8bit CPU of ICF3-Z
12	1	0	1 year, 6 months ago	RISCV-CPU/917	A Homework for Computer Architecture at SJTU
12	2	0	Unknown	ddec/918	Digital Design Express Course
12	9	0	Unknown	VP2motion/919	FPGA based motion controller for RepRap style 3D printers
12	6	0	Unknown	SparkRoad-FPGA/920	None
12	4	0	Unknown	DSITx/921	FPGA implementation of DSITx (single lane) used in conjunction with ipod nano 7th gen display
12	14	0	Unknown	axi-bfm/922	git clone of http://code.google.com/p/axi-bfm/
12	1	0	7 years ago	next186_soc_pc/923	Next186 SoC PC
12	0	0	Unknown	gameboy-sound-chip/924	None
12	3	6	Unknown	loam/925	Loam system models
12	8	0	Unknown	FPGA_NTP_SERVER/926	None
12	5	0	6 years ago	Simple-32bit-ALU-Design/927	A simple, working, 32-bit ALU design.
12	7	0	4 years ago	mriscv_vivado/928	A 32-bit Microcontroller for NEXYS4-DDR fpga based on mriscv.
12	1	0	Unknown	sky-machine/929	An untyped lambda calculus machine designed in FPGA.
12	11	1	Unknown	i2c-master/930	An i2c master controller implemented in Verilog
12	1	0	Unknown	DVGHV/931	Designing Video Game Hardware in Verilog
12	21	0	Unknown	CE202-LC-Lab-Manual/932	Manual and Template Sources of Logic Circuit Laboratory (Verilog Templates)
12	0	0	Unknown	plaid-bib-cpld/933	A replica of the Ad Lib MCA sound card, now with a CPLD instead of the bus interface chip
12	1	0	Unknown	nand2tetris-vhdl/934	nand2tetris files converted to VHDL so I can simulate them on an FPGA
12	0	0	Unknown	tetris-verilog/935	Verilog Tetris
12	4	0	Unknown	FPGA-video-decoder/936	👾 Design and implementation of a video decoder on an Altera Cyclone V FPGA board.
12	3	1	Unknown	uart_dpi/937	DPI module for UART-based console interaction with Verilator simulations
12	10	0	Unknown	nitro-parts-lib-mipi/938	RTL for mipi serialize and deserialize
12	7	0	Unknown	DRUM/939	The Verilog source code for DRUM approximate multiplier.
12	7	0	Unknown	Verilog-Adders/940	Implementing Different Adder Structures in Verilog
12	8	0	Unknown	Chisel-FFT/941	FFT wrriten in Chisel
11	9	0	Unknown	axi-ddr3/942	学习AXI接口，以及xilinx DDR3 IP使用
11	0	0	Unknown	ice-risc/943	RISC CPU by Icenowy
11	0	0	Unknown	lemoncore/944	Simple RISC-V processor for FPGAs 🍋 🤖
11	5	0	Unknown	8bit_MicroComputer_Verilog/945	This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This was developed for the Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
11	3	0	Unknown	FPGA_Vending_Machine/946	东南大学信息学院大三短学期FPGA课程设计——售货机
11	3	0	Unknown	Midi_SynthFpga/947	Sound synthetizer with an fpga
11	6	0	Unknown	parallella-fpga-tutorials/948	A place to store the code for FPGA tutorial projects I have written for the Parallella [http://parallellagram.org]
11	3	0	Unknown	hilotof/949	HiLoTOF -- Hardware-in-the-Loop Test framework for Open FPGAs
11	0	0	Unknown	UART/950	ARM中通过APB总线连接的UART模块
11	4	1	Unknown	FPGA_Spiking_NN/951	CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers
11	0	1	Unknown	miniatom/952	Acorn Atom in minimal configuration for iCE40 HX8K board and ICOboard
11	4	0	Unknown	qemu-hdl-cosim/953	VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
11	0	0	Unknown	MiSTer-Arcade-DigDug/954	FPGA implementation of DigDug arcade game
11	8	0	Unknown	Multiported-RAM/955	Modular Multi-ported SRAM-based Memory
11	6	0	Unknown	Example-Codes-for-Snorkeling-in-Verilog-Bay/956	Example Codes for Snorkeling in Verilog Bay
11	8	0	Unknown	uart/957	Verilog uart receiver and transmitter modules for De0 Nano
11	3	1	Unknown	ecp5_jtag/958	Use ECP5 JTAG port to interact with user design
11	0	0	Unknown	ctf-writeups/959	My CTF writeups
11	1	1	Unknown	tang-nano-lcd/960	Sipeed Tang Nano playground
11	0	0	Unknown	Virtual-Console/961	work in progress of a xterm-256color terminal
11	4	0	Unknown	FPGA-Snappy-Decompressor/962	A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.
11	2	0	Unknown	v8cpu/963	v8cpu is a simple multi-cycle von Neumann architecture 8-bit CPU in under 500 lines of Verilog.
11	5	1	Unknown	lora-modulator/964	None
11	4	0	Unknown	NCL_sandbox/965	Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determined design in a familiar context. The tools used are Icarus verilog and gtkwave.
11	14	0	Unknown	OFDM_802_11/966	None
11	3	0	Unknown	ov/967	None
11	8	0	Unknown	Verilog-Pac-Man/968	Verilog implementation of Pac-Man made for a class's final project
11	3	0	Unknown	panog1_opl3/969	A port of the OPL3 to the Panologic G1 thin client
11	10	0	Unknown	Mustang/970	Top level of PulseRain M10 RTL design
11	6	0	Unknown	OpenProjects/971	None
11	0	0	Unknown	fpga_nes/972	Recreating an NES in verilog
11	12	0	Unknown	FT245_interface/973	Verilog module to communicate with the FT245 interface of an FTDI FT2232H
11	7	0	Unknown	Verilog-SPI-Master/974	A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen
11	4	3	Unknown	ahci_mpi/975	an sata controller using smallest resource.
11	3	0	Unknown	FPGAMAG18/976	FPGA Magazine No.18 - RISC-V
11	6	0	Unknown	XCryptCore/977	Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
11	7	0	Unknown	FIFO_-asynchronous/978	异步FIFO的内部实现
11	11	5	Unknown	papiGB/979	Game Boy Classic fully functional FPGA implementation from scratch
11	3	0	Unknown	crunchy/980	Distributed FPGA Number Crunching for the Masses
11	6	1	Unknown	dvi_lvds/981	DVI to LVDS Verilog converter
11	7	0	Unknown	bbcpu/982	None
11	0	0	Unknown	sub-25-ns-nasdaq-itch-fpga-parser/983	None
11	3	1	Unknown	core_usb_uart/984	USB serial device (CDC-ACM)
11	5	0	Unknown	aq_mipi_csi2rx_ultrascaleplus/985	None
11	176	0	Unknown	ece4750-tut4-verilog/986	ECE 4750 Tutorial 4: Verilog Hardware Description Language
11	1	0	Unknown	v.vga.font8x16/987	Verilog VGA font generator 8 by 16 pixels
11	7	0	Unknown	Zedboard-OLED/988	None
11	6	0	Unknown	Single-Cycle-CPU/989	None
11	3	0	Unknown	rtcclock/990	A Real Time Clock core for FPGA's
11	3	0	Unknown	ECG-feature-extraction-using-DWT/991	Haar wavelet based Discrete wavelet transform for ECG feature extraction in Verilog
11	4	8	Unknown	automatic-chainsaw/992	A custom 16-bit computer
11	2	0	Unknown	bfcpu/993	A simple CPU that runs Br**nf*ck code.
11	3	0	Unknown	HDLBits_Practice_verilog/994	This is a practice of verilog coding
11	4	0	Unknown	USB3_MIPI_CSI2_RX_V2_Crosslink_NX/995	MIPI CSI-2 Camera Sensor Receiver V2 Verilog HDL implementation For any generic FPGA. Tested with IMX219 IMX477 on Lattice Crosslink NX with Hard MIPI PHY. Gbps UVC Video Stream Over USB 3.0 with Cypress FX3, Currently WIP
11	5	0	Unknown	Open-Source-System-on-Chip-Experiment/996	Just experimenting with Open Source SoCs on my Altera dev kit.
11	1	0	Unknown	ZC-RISCV-CORE/997	ZC RISCV CORE
11	9	0	Unknown	Verilog-I2C-Slave/998	Verilog I2C Slave
11	5	1	Unknown	sram/999	Simple sram controller in verilog.
11	5	0	Unknown	numatolib/1000	Demo Library for Numato FPGA Boards