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M68k_LINEE.c
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/*
Copyright © 2019 Michal Schulz <[email protected]>
https://github.com/michalsc
This Source Code Form is subject to the terms of the
Mozilla Public License, v. 2.0. If a copy of the MPL was not distributed
with this file, You can obtain one at http://mozilla.org/MPL/2.0/.
*/
#include "support.h"
#include "M68k.h"
#include "RegisterAllocator.h"
static uint32_t *EMIT_ASR_mem(uint32_t *ptr, uint16_t opcode, uint16_t **m68k_ptr) __attribute__((alias("EMIT_ASL_mem")));
static uint32_t *EMIT_ASL_mem(uint32_t *ptr, uint16_t opcode, uint16_t **m68k_ptr)
{
uint8_t update_mask = M68K_GetSRMask(&(*m68k_ptr)[-1]);
uint8_t direction = (opcode >> 8) & 1;
uint8_t dest = 0xff;
uint8_t tmp = RA_AllocARMRegister(&ptr);
uint8_t ext_words = 0;
ptr = EMIT_LoadFromEffectiveAddress(ptr, 0, &dest, opcode & 0x3f, *m68k_ptr, &ext_words, 1, NULL);
/* Pre-decrement mode */
if ((opcode & 0x38) == 0x20) {
*ptr++ = ldrsh_offset_preindex(dest, tmp, -2);
}
else {
*ptr++ = ldrsh_offset(dest, tmp, 0);
}
#ifdef __aarch64__
if (update_mask & (SR_C | SR_X)) {
if (direction) {
*ptr++ = tst_immed(tmp, 1, 32 - 15);
}
else {
*ptr++ = tst_immed(tmp, 1, 0);
}
}
#endif
if (direction)
{
#ifdef __aarch64__
*ptr++ = lsl(tmp, tmp, 1);
#else
*ptr++ = lsls_immed(tmp, tmp, 17);
*ptr++ = lsr_immed(tmp, tmp, 16);
#endif
}
else
{
#ifdef __aarch64__
*ptr++ = asr(tmp, tmp, 1);
#else
*ptr++ = asrs_immed(tmp, tmp, 1);
#endif
}
if ((opcode & 0x38) == 0x18) {
*ptr++ = strh_offset_postindex(dest, tmp, 2);
}
else {
*ptr++ = strh_offset(dest, tmp, 0);
}
ptr = EMIT_AdvancePC(ptr, 2 * (ext_words + 1));
(*m68k_ptr) += ext_words;
if (update_mask)
{
uint8_t cc = RA_ModifyCC(&ptr);
uint8_t tmp2 = RA_AllocARMRegister(&ptr);
*ptr++ = mov_immed_u16(tmp2, update_mask, 0);
*ptr++ = bic_reg(cc, cc, tmp2, LSL, 0);
if (update_mask & (SR_C | SR_X)) {
*ptr++ = b_cc(A64_CC_EQ, 3);
*ptr++ = mov_immed_u16(tmp2, SR_C | SR_X, 0);
*ptr++ = orr_reg(cc, cc, tmp2, LSL, 0);
}
if (update_mask & (SR_Z | SR_N))
{
*ptr++ = cmn_reg(31, tmp, LSL, 16);
if (update_mask & SR_Z) {
*ptr++ = b_cc(A64_CC_EQ ^ 1, 2);
*ptr++ = orr_immed(cc, cc, 1, (32 - SRB_Z) & 31);
}
if (update_mask & SR_N) {
*ptr++ = b_cc(A64_CC_MI ^ 1, 2);
*ptr++ = orr_immed(cc, cc, 1, (32 - SRB_N) & 31);
}
}
RA_FreeARMRegister(&ptr, tmp2);
// V flag can have non-zero value only for left shifting
if ((update_mask & SR_V) && direction)
{
*ptr++ = eor_reg(tmp, tmp, tmp, LSL, 1);
*ptr++ = tbz(tmp, 16, 2);
*ptr++ = orr_immed(cc, cc, 1, (32 - SRB_V) & 31);
}
}
RA_FreeARMRegister(&ptr, tmp);
RA_FreeARMRegister(&ptr, dest);
return ptr;
}
static uint32_t *EMIT_LSR_mem(uint32_t *ptr, uint16_t opcode, uint16_t **m68k_ptr) __attribute__((alias("EMIT_LSL_mem")));
static uint32_t *EMIT_LSL_mem(uint32_t *ptr, uint16_t opcode, uint16_t **m68k_ptr)
{
uint8_t update_mask = M68K_GetSRMask(&(*m68k_ptr)[-1]);
uint8_t direction = (opcode >> 8) & 1;
uint8_t dest = 0xff;
uint8_t tmp = RA_AllocARMRegister(&ptr);
uint8_t ext_words = 0;
ptr = EMIT_LoadFromEffectiveAddress(ptr, 0, &dest, opcode & 0x3f, *m68k_ptr, &ext_words, 1, NULL);
/* Pre-decrement mode */
if ((opcode & 0x38) == 0x20) {
*ptr++ = ldrh_offset_preindex(dest, tmp, -2);
}
else {
*ptr++ = ldrh_offset(dest, tmp, 0);
}
#ifdef __aarch64__
if (update_mask & (SR_C | SR_X)) {
if (direction) {
*ptr++ = tst_immed(tmp, 1, 32 - 15);
}
else {
*ptr++ = tst_immed(tmp, 1, 0);
}
}
#endif
if (direction)
{
#ifdef __aarch64__
*ptr++ = lsl(tmp, tmp, 1);
#else
*ptr++ = lsls_immed(tmp, tmp, 17);
*ptr++ = lsr_immed(tmp, tmp, 16);
#endif
}
else
{
#ifdef __aarch64__
*ptr++ = lsr(tmp, tmp, 1);
#else
*ptr++ = lsrs_immed(tmp, tmp, 1);
#endif
}
if ((opcode & 0x38) == 0x18) {
*ptr++ = strh_offset_postindex(dest, tmp, 2);
}
else {
*ptr++ = strh_offset(dest, tmp, 0);
}
ptr = EMIT_AdvancePC(ptr, 2 * (ext_words + 1));
(*m68k_ptr) += ext_words;
if (update_mask)
{
#ifdef __aarch64__
uint8_t cc = RA_ModifyCC(&ptr);
uint8_t tmp2 = RA_AllocARMRegister(&ptr);
*ptr++ = mov_immed_u16(tmp2, update_mask, 0);
*ptr++ = bic_reg(cc, cc, tmp2, LSL, 0);
if (update_mask & (SR_C | SR_X)) {
*ptr++ = b_cc(A64_CC_EQ, 3);
*ptr++ = mov_immed_u16(tmp2, SR_C | SR_X, 0);
*ptr++ = orr_reg(cc, cc, tmp2, LSL, 0);
}
RA_FreeARMRegister(&ptr, tmp2);
if (update_mask & (SR_Z | SR_N))
{
*ptr++ = cmn_reg(31, tmp, LSL, 16);
*ptr++ = mov_immed_u16(tmp, update_mask, 0);
if (update_mask & SR_Z) {
*ptr++ = b_cc(A64_CC_EQ ^ 1, 2);
*ptr++ = orr_immed(cc, cc, 1, (32 - SRB_Z) & 31);
}
if (update_mask & SR_N) {
*ptr++ = b_cc(A64_CC_MI ^ 1, 2);
*ptr++ = orr_immed(cc, cc, 1, (32 - SRB_N) & 31);
}
}
#else
M68K_ModifyCC(&ptr);
*ptr++ = bic_immed(REG_SR, REG_SR, update_mask);
if (update_mask & SR_N)
*ptr++ = orr_cc_immed(ARM_CC_MI, REG_SR, REG_SR, SR_N);
if (update_mask & SR_Z)
*ptr++ = orr_cc_immed(ARM_CC_EQ, REG_SR, REG_SR, SR_Z);
if (update_mask & (SR_X | SR_C))
*ptr++ = orr_cc_immed(ARM_CC_CS, REG_SR, REG_SR, SR_X | SR_C);
#endif
}
RA_FreeARMRegister(&ptr, tmp);
RA_FreeARMRegister(&ptr, dest);
return ptr;
}
static uint32_t *EMIT_ROXR_mem(uint32_t *ptr, uint16_t opcode, uint16_t **m68k_ptr) __attribute__((alias("EMIT_ROXL_mem")));
static uint32_t *EMIT_ROXL_mem(uint32_t *ptr, uint16_t opcode, uint16_t **m68k_ptr)
{
uint8_t update_mask = M68K_GetSRMask(&(*m68k_ptr)[-1]);
uint8_t direction = (opcode >> 8) & 1;
uint8_t dest = 0xff;
uint8_t ext_words = 0;
uint8_t cc = RA_ModifyCC(&ptr);
uint8_t tmp = RA_AllocARMRegister(&ptr);
ptr = EMIT_LoadFromEffectiveAddress(ptr, 0, &dest, opcode & 0x3f, *m68k_ptr, &ext_words, 1, NULL);
if ((opcode & 0x38) == 0x20) {
*ptr++ = ldrh_offset_preindex(dest, tmp, -2);
}
else {
*ptr++ = ldrh_offset(dest, tmp, 0);
}
/* Test X flag, push the flag value into tmp register */
*ptr++ = tst_immed(cc, 1, 32 - SRB_X);
*ptr++ = b_cc(A64_CC_EQ, 2);
if (direction) {
*ptr++ = orr_immed(tmp, tmp, 1, 1);
*ptr++ = ror(tmp, tmp, 31);
}
else {
*ptr++ = orr_immed(tmp, tmp, 1, 16);
*ptr++ = ror(tmp, tmp, 1);
}
if ((opcode & 0x38) == 0x18) {
*ptr++ = strh_offset_postindex(dest, tmp, 2);
}
else {
*ptr++ = strh_offset(dest, tmp, 0);
}
ptr = EMIT_AdvancePC(ptr, 2 * (ext_words + 1));
(*m68k_ptr) += ext_words;
if (update_mask)
{
uint8_t tmp2 = RA_AllocARMRegister(&ptr);
uint8_t update_mask_copy = update_mask;
if (update_mask & (SR_Z | SR_N))
{
*ptr++ = cmn_reg(31, tmp, LSL, 16);
ptr = EMIT_GetNZ00(ptr, cc, &update_mask);
}
else if (update_mask & SR_V) {
*ptr++ = bic_immed(cc, cc, 1, 32 - SRB_V);
}
if (update_mask_copy & SR_XC) {
if (direction) {
*ptr++ = bfxil(cc, tmp, 16, 1);
}
else {
*ptr++ = bfxil(cc, tmp, 31, 1);
}
if (update_mask_copy & SR_X) {
*ptr++ = bfi(cc, cc, 4, 1);
}
}
RA_FreeARMRegister(&ptr, tmp2);
}
RA_FreeARMRegister(&ptr, tmp);
RA_FreeARMRegister(&ptr, dest);
return ptr;
}
static uint32_t *EMIT_ROR_mem(uint32_t *ptr, uint16_t opcode, uint16_t **m68k_ptr) __attribute__((alias("EMIT_ROL_mem")));
static uint32_t *EMIT_ROL_mem(uint32_t *ptr, uint16_t opcode, uint16_t **m68k_ptr)
{
uint8_t update_mask = M68K_GetSRMask(&(*m68k_ptr)[-1]);
uint8_t direction = (opcode >> 8) & 1;
uint8_t dest = 0xff;
uint8_t tmp = RA_AllocARMRegister(&ptr);
uint8_t ext_words = 0;
ptr = EMIT_LoadFromEffectiveAddress(ptr, 0, &dest, opcode & 0x3f, *m68k_ptr, &ext_words, 1, NULL);
if ((opcode & 0x38) == 0x20) {
*ptr++ = ldrh_offset_preindex(dest, tmp, -2);
}
else {
*ptr++ = ldrh_offset(dest, tmp, 0);
}
*ptr++ = bfi(tmp, tmp, 16, 16);
if (direction)
{
*ptr++ = ror(tmp, tmp, 32 - 1);
}
else
{
*ptr++ = ror(tmp, tmp, 1);
}
if ((opcode & 0x38) == 0x18) {
*ptr++ = strh_offset_postindex(dest, tmp, 2);
}
else {
*ptr++ = strh_offset(dest, tmp, 0);
}
ptr = EMIT_AdvancePC(ptr, 2 * (ext_words + 1));
(*m68k_ptr) += ext_words;
if (update_mask)
{
uint8_t tmp2 = RA_AllocARMRegister(&ptr);
uint8_t cc = RA_ModifyCC(&ptr);
if (update_mask & (SR_Z | SR_N))
{
*ptr++ = cmn_reg(31, tmp, LSL, 16);
}
*ptr++ = mov_immed_u16(tmp2, update_mask, 0);
*ptr++ = bic_reg(cc, cc, tmp2, LSL, 0);
if (update_mask & SR_Z) {
*ptr++ = b_cc(A64_CC_EQ ^ 1, 2);
*ptr++ = orr_immed(cc, cc, 1, (32 - SRB_Z) & 31);
}
if (update_mask & SR_N) {
*ptr++ = b_cc(A64_CC_MI ^ 1, 2);
*ptr++ = orr_immed(cc, cc, 1, (32 - SRB_N) & 31);
}
if (update_mask & (SR_C)) {
if (direction) {
*ptr++ = tst_immed(tmp, 1, 16);
}
else {
*ptr++ = tst_immed(tmp, 1, 1);
}
*ptr++ = b_cc(A64_CC_EQ, 2);
*ptr++ = orr_immed(cc, cc, 1, 31 & (32 - SRB_C));
}
RA_FreeARMRegister(&ptr, tmp2);
}
RA_FreeARMRegister(&ptr, tmp);
RA_FreeARMRegister(&ptr, dest);
return ptr;
}
static uint32_t *EMIT_ASR_reg(uint32_t *ptr, uint16_t opcode, uint16_t **m68k_ptr) __attribute__((alias("EMIT_ASL_reg")));
static uint32_t *EMIT_ASL_reg(uint32_t *ptr, uint16_t opcode, uint16_t **m68k_ptr)
{
uint8_t cc = RA_ModifyCC(&ptr);
uint8_t update_mask = M68K_GetSRMask(&(*m68k_ptr)[-1]);
uint8_t shift = (opcode >> 9) & 7;
uint8_t size = 1 << ((opcode >> 6) & 3);
uint8_t reg = RA_MapM68kRegister(&ptr, opcode & 7);
uint8_t tmp = RA_AllocARMRegister(&ptr);
uint8_t direction = (opcode >> 8) & 1;
uint32_t *tmpptr_1;
uint32_t *tmpptr_2;
uint8_t shiftreg_orig = RA_AllocARMRegister(&ptr);
uint8_t reg_orig = RA_AllocARMRegister(&ptr);
uint8_t mask = RA_AllocARMRegister(&ptr);
RA_SetDirtyM68kRegister(&ptr, opcode & 7);
uint8_t shiftreg = RA_MapM68kRegister(&ptr, shift);
// Check shift size 0 - in that case no bit shifting is necessary, clear VC flags, update NZ, leave X
*ptr++ = ands_immed(shiftreg_orig, shiftreg, 6, 0);
tmpptr_1 = ptr;
*ptr++ = b_cc(A64_CC_NE, 0);
// If N and/or Z need to be updated, do it and clear CV. No further actions are necessary
if (update_mask & SR_NZ) {
uint8_t update_mask_copy = update_mask;
switch (size) {
case 4:
*ptr++ = cmn_reg(31, reg, LSL, 0);
break;
case 2:
*ptr++ = cmn_reg(31, reg, LSL, 16);
break;
case 1:
*ptr++ = cmn_reg(31, reg, LSL, 24);
break;
}
ptr = EMIT_GetNZ00(ptr, cc, &update_mask_copy);
}
else if (update_mask & SR_VC) {
// Only V or C need to be updated. Clear both
*ptr++ = bic_immed(cc, cc, 2, 0);
}
tmpptr_2 = ptr;
// Skip further bit shifting totally
*ptr++ = b_cc(A64_CC_AL, 0);
if ((ptr - tmpptr_1) != 2) {
*tmpptr_1 = b_cc(A64_CC_NE, ptr - tmpptr_1);
}
else {
ptr--;
tmpptr_2--;
tmpptr_1 = NULL;
}
if (direction)
{
if (update_mask & SR_V)
{
*ptr++ = mov64_immed_u16(mask, 0x8000, 3);
*ptr++ = asrv64(mask, mask, shiftreg_orig);
switch (size)
{
case 4:
*ptr++ = lsr64(mask, mask, 32);
*ptr++ = mov_reg(reg_orig, reg);
break;
case 2:
*ptr++ = lsr64(mask, mask, 32+16);
*ptr++ = and_immed(reg_orig, reg, 16, 0);
break;
case 1:
*ptr++ = lsr64(mask, mask, 32 + 24);
*ptr++ = and_immed(reg_orig, reg, 8, 0);
break;
}
}
switch(size)
{
case 4:
*ptr++ = lslv64(tmp, reg, shiftreg);
*ptr++ = mov_reg(reg, tmp);
if (update_mask & (SR_C | SR_X)) {
*ptr++ = tst64_immed(tmp, 1, 32, 1);
}
break;
case 2:
*ptr++ = lslv64(tmp, reg, shiftreg);
if (update_mask & (SR_C | SR_X)) {
*ptr++ = tst_immed(tmp, 1, 16);
}
*ptr++ = bfi(reg, tmp, 0, 16);
break;
case 1:
*ptr++ = lslv64(tmp, reg, shiftreg);
if (update_mask & (SR_C | SR_X)) {
*ptr++ = tst_immed(tmp, 1, 24);
}
*ptr++ = bfi(reg, tmp, 0, 8);
break;
}
}
else
{
uint8_t mask = RA_AllocARMRegister(&ptr);
if (update_mask & (SR_C | SR_X))
{
uint8_t t = RA_AllocARMRegister(&ptr);
*ptr++ = sub_immed(t, shiftreg, 1);
*ptr++ = mov_immed_u16(mask, 1, 0);
*ptr++ = lslv64(mask, mask, t);
RA_FreeARMRegister(&ptr, t);
}
switch (size)
{
case 4:
*ptr++ = sxtw64(tmp, reg);
if (update_mask & (SR_C | SR_X))
{
*ptr++ = ands64_reg(31, tmp, mask, LSL, 0);
}
*ptr++ = asrv64(tmp, tmp, shiftreg);
*ptr++ = mov_reg(reg, tmp);
break;
case 2:
*ptr++ = sxth64(tmp, reg);
if (update_mask & (SR_C | SR_X))
{
*ptr++ = ands64_reg(31, tmp, mask, LSL, 0);
}
*ptr++ = asrv64(tmp, tmp, shiftreg);
*ptr++ = bfi(reg, tmp, 0, 16);
break;
case 1:
*ptr++ = sxtb64(tmp, reg);
if (update_mask & (SR_C | SR_X))
{
*ptr++ = ands64_reg(31, tmp, mask, LSL, 0);
}
*ptr++ = asrv64(tmp, tmp, shiftreg);
*ptr++ = bfi(reg, tmp, 0, 8);
break;
}
RA_FreeARMRegister(&ptr, mask);
}
if (update_mask)
{
uint8_t tmp2 = RA_AllocARMRegister(&ptr);
*ptr++ = mov_immed_u16(tmp2, update_mask, 0);
*ptr++ = bic_reg(cc, cc, tmp2, LSL, 0);
if (update_mask & (SR_C | SR_X)) {
*ptr++ = b_cc(A64_CC_EQ, 3);
*ptr++ = mov_immed_u16(tmp2, SR_C | SR_X, 0);
*ptr++ = orr_reg(cc, cc, tmp2, LSL, 0);
}
RA_FreeARMRegister(&ptr, tmp2);
if (direction && (update_mask & SR_V)) {
*ptr++ = ands_reg(31, reg_orig, mask, LSL, 0);
*ptr++ = b_cc(A64_CC_EQ, 7);
*ptr++ = cmp_immed(shiftreg_orig, size == 4 ? 32 : (size == 2 ? 16 : 8));
*ptr++ = b_cc(A64_CC_GE, 4);
*ptr++ = eor_reg(reg_orig, reg_orig, mask, LSL, 0);
*ptr++ = ands_reg(31, reg_orig, mask, LSL, 0);
*ptr++ = b_cc(A64_CC_EQ, 2);
*ptr++ = orr_immed(cc, cc, 1, 31 & (32 - SRB_V));
}
if (update_mask & (SR_Z | SR_N))
{
switch(size)
{
case 4:
*ptr++ = cmn_reg(31, reg, LSL, 0);
break;
case 2:
*ptr++ = cmn_reg(31, tmp, LSL, 16);
break;
case 1:
*ptr++ = cmn_reg(31, tmp, LSL, 24);
break;
}
if (update_mask & SR_Z) {
*ptr++ = b_cc(A64_CC_EQ ^ 1, 2);
*ptr++ = orr_immed(cc, cc, 1, (32 - SRB_Z) & 31);
}
if (update_mask & SR_N) {
*ptr++ = b_cc(A64_CC_MI ^ 1, 2);
*ptr++ = orr_immed(cc, cc, 1, (32 - SRB_N) & 31);
}
}
}
if (tmpptr_1 != NULL) {
*tmpptr_2 = b_cc(A64_CC_AL, ptr - tmpptr_2);
}
else {
*tmpptr_2 = b_cc(A64_CC_EQ, ptr - tmpptr_2);
}
ptr = EMIT_AdvancePC(ptr, 2);
RA_FreeARMRegister(&ptr, tmp);
RA_FreeARMRegister(&ptr, mask);
RA_FreeARMRegister(&ptr, shiftreg_orig);
RA_FreeARMRegister(&ptr, reg_orig);
return ptr;
}
static uint32_t *EMIT_ASR(uint32_t *ptr, uint16_t opcode, uint16_t **m68k_ptr) __attribute__((alias("EMIT_ASL")));
static uint32_t *EMIT_ASL(uint32_t *ptr, uint16_t opcode, uint16_t **m68k_ptr)
{
uint8_t update_mask = M68K_GetSRMask(&(*m68k_ptr)[-1]);
uint8_t shift = (opcode >> 9) & 7;
uint8_t size = 1 << ((opcode >> 6) & 3);
uint8_t reg = RA_MapM68kRegister(&ptr, opcode & 7);
uint8_t tmp = RA_AllocARMRegister(&ptr);
uint8_t direction = (opcode >> 8) & 1;
uint8_t cc = RA_ModifyCC(&ptr);
RA_SetDirtyM68kRegister(&ptr, opcode & 7);
if (!shift) shift = 8;
if (direction && (update_mask & SR_V))
{
uint8_t tmp_reg = RA_AllocARMRegister(&ptr);
int rot = (size == 4) ? 0 : (size == 2) ? 16 : 24;
int width = shift + 1;
if (size == 1 && width > 8)
width = 8;
*ptr++ = bic_immed(cc, cc, 1, 31 & (32 - SRB_V));
*ptr++ = ands_immed(tmp_reg, reg, width, width + rot);
*ptr++ = b_cc(A64_CC_EQ, (size == 1 && shift == 8) ? 2 : 5);
if (!(size == 1 && shift == 8)) {
*ptr++ = eor_immed(tmp_reg, tmp_reg, width, width + rot);
*ptr++ = ands_immed(tmp_reg, tmp_reg, width, width + rot);
*ptr++ = b_cc(A64_CC_EQ, 2);
}
*ptr++ = orr_immed(cc, cc, 1, 31 & (32 - SRB_V));
update_mask &= ~SR_V;
RA_FreeARMRegister(&ptr, tmp_reg);
}
if (update_mask & (SR_C | SR_X)) {
if (direction) {
switch (size) {
case 4:
*ptr++ = tst_immed(reg, 1, shift);
break;
case 2:
*ptr++ = tst_immed(reg, 1, 16 + shift);
break;
case 1:
*ptr++ = tst_immed(reg, 1, 31 & (24 + shift));
break;
}
}
else {
*ptr++ = tst_immed(reg, 1, 31 & (33 - shift));
}
}
if (direction)
{
switch (size)
{
case 4:
*ptr++ = lsl(reg, reg, shift);
break;
case 2:
*ptr++ = lsl(tmp, reg, shift);
*ptr++ = bfi(reg, tmp, 0, 16);
break;
case 1:
*ptr++ = lsl(tmp, reg, shift);
*ptr++ = bfi(reg, tmp, 0, 8);
break;
}
}
else
{
switch (size)
{
case 4:
*ptr++ = asr(reg, reg, shift);
break;
case 2:
*ptr++ = sxth(tmp, reg);
*ptr++ = asr(tmp, tmp, shift);
*ptr++ = bfi(reg, tmp, 0, 16);
break;
case 1:
*ptr++ = sxtb(tmp, reg);
*ptr++ = asr(tmp, tmp, shift);
*ptr++ = bfi(reg, tmp, 0, 8);
break;
}
}
ptr = EMIT_AdvancePC(ptr, 2);
if (update_mask)
{
uint8_t tmp2 = RA_AllocARMRegister(&ptr);
*ptr++ = mov_immed_u16(tmp2, update_mask, 0);
*ptr++ = bic_reg(cc, cc, tmp2, LSL, 0);
if (update_mask & (SR_C | SR_X)) {
*ptr++ = b_cc(A64_CC_EQ, 3);
*ptr++ = mov_immed_u16(tmp2, SR_C | SR_X, 0);
*ptr++ = orr_reg(cc, cc, tmp2, LSL, 0);
}
RA_FreeARMRegister(&ptr, tmp2);
if (update_mask & (SR_Z | SR_N))
{
switch(size)
{
case 4:
*ptr++ = cmn_reg(31, reg, LSL, 0);
break;
case 2:
*ptr++ = cmn_reg(31, tmp, LSL, 16);
break;
case 1:
*ptr++ = cmn_reg(31, tmp, LSL, 24);
break;
}
if (update_mask & SR_Z) {
*ptr++ = b_cc(A64_CC_EQ ^ 1, 2);
*ptr++ = orr_immed(cc, cc, 1, (32 - SRB_Z) & 31);
}
if (update_mask & SR_N) {
*ptr++ = b_cc(A64_CC_MI ^ 1, 2);
*ptr++ = orr_immed(cc, cc, 1, (32 - SRB_N) & 31);
}
}
}
RA_FreeARMRegister(&ptr, tmp);
return ptr;
}
static uint32_t *EMIT_LSR_reg(uint32_t *ptr, uint16_t opcode, uint16_t **m68k_ptr) __attribute__((alias("EMIT_LSL_reg")));
static uint32_t *EMIT_LSL_reg(uint32_t *ptr, uint16_t opcode, uint16_t **m68k_ptr)
{
uint8_t cc = RA_ModifyCC(&ptr);
uint8_t update_mask = M68K_GetSRMask(&(*m68k_ptr)[-1]);
uint8_t direction = (opcode >> 8) & 1;
uint8_t shift = (opcode >> 9) & 7;
uint8_t size = 1 << ((opcode >> 6) & 3);
uint8_t reg = RA_MapM68kRegister(&ptr, opcode & 7);
uint8_t tmp = RA_AllocARMRegister(&ptr);
uint32_t *tmpptr_1;
uint32_t *tmpptr_2;
RA_SetDirtyM68kRegister(&ptr, opcode & 7);
uint8_t shiftreg = RA_MapM68kRegister(&ptr, shift);
// Check shift size 0 - in that case no bit shifting is necessary, clear VC flags, update NZ, leave X
*ptr++ = ands_immed(31, shiftreg, 6, 0);
tmpptr_1 = ptr;
*ptr++ = b_cc(A64_CC_NE, 0);
// If V and/or Z need to be updated, do it and clear CV. No further actions are necessary
if (update_mask & SR_NZ) {
uint8_t update_mask_copy = update_mask;
switch (size) {
case 4:
*ptr++ = cmn_reg(31, reg, LSL, 0);
break;
case 2:
*ptr++ = cmn_reg(31, reg, LSL, 16);
break;
case 1:
*ptr++ = cmn_reg(31, reg, LSL, 24);
break;
}
ptr = EMIT_GetNZ00(ptr, cc, &update_mask_copy);
}
else if (update_mask & SR_VC) {
// Only V or C need to be updated. Clear both
*ptr++ = bic_immed(cc, cc, 2, 0);
}
tmpptr_2 = ptr;
// Skip further bit shifting totally
*ptr++ = b_cc(A64_CC_AL, 0);
if ((ptr - tmpptr_1) != 2) {
*tmpptr_1 = b_cc(A64_CC_NE, ptr - tmpptr_1);
}
else {
ptr--;
tmpptr_2--;
tmpptr_1 = NULL;
}
if (direction)
{
switch (size)
{
case 4:
#ifdef __aarch64__
*ptr++ = lslv64(tmp, reg, shiftreg);
*ptr++ = mov_reg(reg, tmp);
if (update_mask & (SR_C | SR_X)) {
*ptr++ = tst64_immed(tmp, 1, 32, 1);
}
#else
*ptr++ = lsls_reg(reg, reg, shiftreg);
#endif
break;
case 2:
#ifdef __aarch64__
*ptr++ = lslv64(tmp, reg, shiftreg);
if (update_mask & (SR_C | SR_X)) {
*ptr++ = tst_immed(tmp, 1, 16);
}
#else
*ptr++ = mov_reg_shift(tmp, reg, 16);
*ptr++ = lsls_reg(tmp, tmp, shiftreg);
*ptr++ = lsr_immed(tmp, tmp, 16);
#endif
*ptr++ = bfi(reg, tmp, 0, 16);
break;
case 1:
#ifdef __aarch64__
*ptr++ = lslv64(tmp, reg, shiftreg);
if (update_mask & (SR_C | SR_X)) {
*ptr++ = tst_immed(tmp, 1, 24);
}
#else
*ptr++ = mov_reg_shift(tmp, reg, 24);
*ptr++ = lsls_reg(tmp, tmp, shiftreg);
*ptr++ = lsr_immed(tmp, tmp, 24);
#endif
*ptr++ = bfi(reg, tmp, 0, 8);
break;
}
}
else
{
uint8_t mask = RA_AllocARMRegister(&ptr);
#ifdef __aarch64__
if (update_mask & (SR_C | SR_X))
{
uint8_t t = RA_AllocARMRegister(&ptr);
*ptr++ = sub_immed(t, shiftreg, 1);
*ptr++ = mov_immed_u16(mask, 1, 0);
*ptr++ = lslv64(mask, mask, t);
RA_FreeARMRegister(&ptr, t);
}
#endif
switch (size)
{
case 4:
#ifdef __aarch64__
*ptr++ = mov_reg(tmp, reg);
if (update_mask & (SR_C | SR_X))
{
*ptr++ = ands_reg(31, tmp, mask, LSL, 0);
}
*ptr++ = lsrv64(tmp, tmp, shiftreg);
*ptr++ = mov_reg(reg, tmp);
#else
*ptr++ = lsrs_reg(reg, reg, shiftreg);
#endif
break;
case 2:
#ifdef __aarch64__
*ptr++ = uxth(tmp, reg);
if (update_mask & (SR_C | SR_X))
{
*ptr++ = ands_reg(31, tmp, mask, LSL, 0);
}
*ptr++ = lsrv64(tmp, tmp, shiftreg);
#else
*ptr++ = uxth(tmp, reg, 0);
*ptr++ = lsrs_reg(tmp, tmp, shiftreg);
#endif
*ptr++ = bfi(reg, tmp, 0, 16);
break;
case 1:
#ifdef __aarch64__
*ptr++ = uxtb(tmp, reg);
if (update_mask & (SR_C | SR_X))
{
*ptr++ = ands_reg(31, tmp, mask, LSL, 0);
}
*ptr++ = lsrv64(tmp, tmp, shiftreg);
#else
*ptr++ = uxtb(tmp, reg, 0);
*ptr++ = lsrs_reg(tmp, tmp, shiftreg);
#endif
*ptr++ = bfi(reg, tmp, 0, 8);
break;
}
RA_FreeARMRegister(&ptr, mask);
}
if (update_mask)
{
#ifdef __aarch64__
uint8_t tmp2 = RA_AllocARMRegister(&ptr);
*ptr++ = mov_immed_u16(tmp2, update_mask, 0);
*ptr++ = bic_reg(cc, cc, tmp2, LSL, 0);
if (update_mask & (SR_C | SR_X)) {
*ptr++ = b_cc(A64_CC_EQ, 3);
*ptr++ = mov_immed_u16(tmp2, SR_C | SR_X, 0);
*ptr++ = orr_reg(cc, cc, tmp2, LSL, 0);
}
RA_FreeARMRegister(&ptr, tmp2);
if (update_mask & (SR_Z | SR_N))
{
switch(size)
{
case 4:
*ptr++ = cmn_reg(31, reg, LSL, 0);
break;
case 2:
*ptr++ = cmn_reg(31, tmp, LSL, 16);
break;
case 1:
*ptr++ = cmn_reg(31, tmp, LSL, 24);
break;
}
if (update_mask & SR_Z) {
*ptr++ = b_cc(A64_CC_EQ ^ 1, 2);
*ptr++ = orr_immed(cc, cc, 1, (32 - SRB_Z) & 31);
}
if (update_mask & SR_N) {
*ptr++ = b_cc(A64_CC_MI ^ 1, 2);
*ptr++ = orr_immed(cc, cc, 1, (32 - SRB_N) & 31);
}
}
#else
M68K_ModifyCC(&ptr);
*ptr++ = bic_immed(REG_SR, REG_SR, update_mask);
if (update_mask & SR_N)
*ptr++ = orr_cc_immed(ARM_CC_MI, REG_SR, REG_SR, SR_N);
if (update_mask & SR_Z)
*ptr++ = orr_cc_immed(ARM_CC_EQ, REG_SR, REG_SR, SR_Z);
if (update_mask & (SR_X | SR_C))
*ptr++ = orr_cc_immed(ARM_CC_CS, REG_SR, REG_SR, SR_X | SR_C);
#endif
}
if (tmpptr_1 != NULL) {
*tmpptr_2 = b_cc(A64_CC_AL, ptr - tmpptr_2);
}
else {
*tmpptr_2 = b_cc(A64_CC_EQ, ptr - tmpptr_2);
}
ptr = EMIT_AdvancePC(ptr, 2);
RA_FreeARMRegister(&ptr, tmp);
return ptr;
}
static uint32_t *EMIT_LSR(uint32_t *ptr, uint16_t opcode, uint16_t **m68k_ptr) __attribute__((alias("EMIT_LSL")));
static uint32_t *EMIT_LSL(uint32_t *ptr, uint16_t opcode, uint16_t **m68k_ptr)
{
uint8_t update_mask = M68K_GetSRMask(&(*m68k_ptr)[-1]);
uint8_t direction = (opcode >> 8) & 1;
uint8_t shift = (opcode >> 9) & 7;
uint8_t size = 1 << ((opcode >> 6) & 3);
uint8_t reg = RA_MapM68kRegister(&ptr, opcode & 7);
uint8_t tmp = RA_AllocARMRegister(&ptr);
RA_SetDirtyM68kRegister(&ptr, opcode & 7);
if (!shift)
shift = 8;
if (update_mask & (SR_C | SR_X)) {
if (direction) {
switch (size) {
case 4:
*ptr++ = tst_immed(reg, 1, shift);
break;
case 2:
*ptr++ = tst_immed(reg, 1, 16 + shift);
break;
case 1:
*ptr++ = tst_immed(reg, 1, 31 & (24 + shift));
break;
}
}
else {
*ptr++ = tst_immed(reg, 1, 31 & (33 - shift));
}
}
if (direction)