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amd64-tdep.c
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/* Target-dependent code for AMD64.
Copyright (C) 2001-2024 Free Software Foundation, Inc.
Contributed by Jiri Smid, SuSE Labs.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "extract-store-integer.h"
#include "language.h"
#include "opcode/i386.h"
#include "dis-asm.h"
#include "arch-utils.h"
#include "dummy-frame.h"
#include "frame.h"
#include "frame-base.h"
#include "frame-unwind.h"
#include "inferior.h"
#include "infrun.h"
#include "cli/cli-cmds.h"
#include "gdbcore.h"
#include "objfiles.h"
#include "regcache.h"
#include "regset.h"
#include "symfile.h"
#include "disasm.h"
#include "amd64-tdep.h"
#include "i387-tdep.h"
#include "gdbsupport/x86-xstate.h"
#include <algorithm>
#include "target-descriptions.h"
#include "arch/amd64.h"
#include "producer.h"
#include "ax.h"
#include "ax-gdb.h"
#include "gdbsupport/byte-vector.h"
#include "osabi.h"
#include "x86-tdep.h"
#include "amd64-ravenscar-thread.h"
#include "gdbsupport/selftest.h"
/* Note that the AMD64 architecture was previously known as x86-64.
The latter is (forever) engraved into the canonical system name as
returned by config.guess, and used as the name for the AMD64 port
of GNU/Linux. The BSD's have renamed their ports to amd64; they
don't like to shout. For GDB we prefer the amd64_-prefix over the
x86_64_-prefix since it's so much easier to type. */
/* Register information. */
static const char * const amd64_register_names[] =
{
"rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
/* %r8 is indeed register number 8. */
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
/* %st0 is register number 24. */
"st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
"fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
/* %xmm0 is register number 40. */
"xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
"xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
"mxcsr",
};
static const char * const amd64_ymm_names[] =
{
"ymm0", "ymm1", "ymm2", "ymm3",
"ymm4", "ymm5", "ymm6", "ymm7",
"ymm8", "ymm9", "ymm10", "ymm11",
"ymm12", "ymm13", "ymm14", "ymm15"
};
static const char * const amd64_ymm_avx512_names[] =
{
"ymm16", "ymm17", "ymm18", "ymm19",
"ymm20", "ymm21", "ymm22", "ymm23",
"ymm24", "ymm25", "ymm26", "ymm27",
"ymm28", "ymm29", "ymm30", "ymm31"
};
static const char * const amd64_ymmh_names[] =
{
"ymm0h", "ymm1h", "ymm2h", "ymm3h",
"ymm4h", "ymm5h", "ymm6h", "ymm7h",
"ymm8h", "ymm9h", "ymm10h", "ymm11h",
"ymm12h", "ymm13h", "ymm14h", "ymm15h"
};
static const char * const amd64_ymmh_avx512_names[] =
{
"ymm16h", "ymm17h", "ymm18h", "ymm19h",
"ymm20h", "ymm21h", "ymm22h", "ymm23h",
"ymm24h", "ymm25h", "ymm26h", "ymm27h",
"ymm28h", "ymm29h", "ymm30h", "ymm31h"
};
static const char * const amd64_k_names[] =
{
"k0", "k1", "k2", "k3",
"k4", "k5", "k6", "k7"
};
static const char * const amd64_zmmh_names[] =
{
"zmm0h", "zmm1h", "zmm2h", "zmm3h",
"zmm4h", "zmm5h", "zmm6h", "zmm7h",
"zmm8h", "zmm9h", "zmm10h", "zmm11h",
"zmm12h", "zmm13h", "zmm14h", "zmm15h",
"zmm16h", "zmm17h", "zmm18h", "zmm19h",
"zmm20h", "zmm21h", "zmm22h", "zmm23h",
"zmm24h", "zmm25h", "zmm26h", "zmm27h",
"zmm28h", "zmm29h", "zmm30h", "zmm31h"
};
static const char * const amd64_zmm_names[] =
{
"zmm0", "zmm1", "zmm2", "zmm3",
"zmm4", "zmm5", "zmm6", "zmm7",
"zmm8", "zmm9", "zmm10", "zmm11",
"zmm12", "zmm13", "zmm14", "zmm15",
"zmm16", "zmm17", "zmm18", "zmm19",
"zmm20", "zmm21", "zmm22", "zmm23",
"zmm24", "zmm25", "zmm26", "zmm27",
"zmm28", "zmm29", "zmm30", "zmm31"
};
static const char * const amd64_xmm_avx512_names[] = {
"xmm16", "xmm17", "xmm18", "xmm19",
"xmm20", "xmm21", "xmm22", "xmm23",
"xmm24", "xmm25", "xmm26", "xmm27",
"xmm28", "xmm29", "xmm30", "xmm31"
};
static const char * const amd64_pkeys_names[] = {
"pkru"
};
/* DWARF Register Number Mapping as defined in the System V psABI,
section 3.6. */
static int amd64_dwarf_regmap[] =
{
/* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
/* Frame Pointer Register RBP. */
AMD64_RBP_REGNUM,
/* Stack Pointer Register RSP. */
AMD64_RSP_REGNUM,
/* Extended Integer Registers 8 - 15. */
AMD64_R8_REGNUM, /* %r8 */
AMD64_R9_REGNUM, /* %r9 */
AMD64_R10_REGNUM, /* %r10 */
AMD64_R11_REGNUM, /* %r11 */
AMD64_R12_REGNUM, /* %r12 */
AMD64_R13_REGNUM, /* %r13 */
AMD64_R14_REGNUM, /* %r14 */
AMD64_R15_REGNUM, /* %r15 */
/* Return Address RA. Mapped to RIP. */
AMD64_RIP_REGNUM,
/* SSE Registers 0 - 7. */
AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
/* Extended SSE Registers 8 - 15. */
AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
/* Floating Point Registers 0-7. */
AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
/* MMX Registers 0 - 7.
We have to handle those registers specifically, as their register
number within GDB depends on the target (or they may even not be
available at all). */
-1, -1, -1, -1, -1, -1, -1, -1,
/* Control and Status Flags Register. */
AMD64_EFLAGS_REGNUM,
/* Selector Registers. */
AMD64_ES_REGNUM,
AMD64_CS_REGNUM,
AMD64_SS_REGNUM,
AMD64_DS_REGNUM,
AMD64_FS_REGNUM,
AMD64_GS_REGNUM,
-1,
-1,
/* Segment Base Address Registers. */
-1,
-1,
-1,
-1,
/* Special Selector Registers. */
-1,
-1,
/* Floating Point Control Registers. */
AMD64_MXCSR_REGNUM,
AMD64_FCTRL_REGNUM,
AMD64_FSTAT_REGNUM,
/* XMM16-XMM31. */
AMD64_XMM16_REGNUM + 0, AMD64_XMM16_REGNUM + 1,
AMD64_XMM16_REGNUM + 2, AMD64_XMM16_REGNUM + 3,
AMD64_XMM16_REGNUM + 4, AMD64_XMM16_REGNUM + 5,
AMD64_XMM16_REGNUM + 6, AMD64_XMM16_REGNUM + 7,
AMD64_XMM16_REGNUM + 8, AMD64_XMM16_REGNUM + 9,
AMD64_XMM16_REGNUM + 10, AMD64_XMM16_REGNUM + 11,
AMD64_XMM16_REGNUM + 12, AMD64_XMM16_REGNUM + 13,
AMD64_XMM16_REGNUM + 14, AMD64_XMM16_REGNUM + 15,
/* Reserved. */
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
/* Mask Registers. */
AMD64_K0_REGNUM + 0, AMD64_K0_REGNUM + 1,
AMD64_K0_REGNUM + 2, AMD64_K0_REGNUM + 3,
AMD64_K0_REGNUM + 4, AMD64_K0_REGNUM + 5,
AMD64_K0_REGNUM + 6, AMD64_K0_REGNUM + 7
};
static const int amd64_dwarf_regmap_len =
(sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
/* Convert DWARF register number REG to the appropriate register
number used by GDB. */
static int
amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
int ymm0_regnum = tdep->ymm0_regnum;
int regnum = -1;
if (reg >= 0 && reg < amd64_dwarf_regmap_len)
regnum = amd64_dwarf_regmap[reg];
if (ymm0_regnum >= 0 && i386_xmm_regnum_p (gdbarch, regnum))
regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);
return regnum;
}
/* Map architectural register numbers to gdb register numbers. */
static const int amd64_arch_regmap[16] =
{
AMD64_RAX_REGNUM, /* %rax */
AMD64_RCX_REGNUM, /* %rcx */
AMD64_RDX_REGNUM, /* %rdx */
AMD64_RBX_REGNUM, /* %rbx */
AMD64_RSP_REGNUM, /* %rsp */
AMD64_RBP_REGNUM, /* %rbp */
AMD64_RSI_REGNUM, /* %rsi */
AMD64_RDI_REGNUM, /* %rdi */
AMD64_R8_REGNUM, /* %r8 */
AMD64_R9_REGNUM, /* %r9 */
AMD64_R10_REGNUM, /* %r10 */
AMD64_R11_REGNUM, /* %r11 */
AMD64_R12_REGNUM, /* %r12 */
AMD64_R13_REGNUM, /* %r13 */
AMD64_R14_REGNUM, /* %r14 */
AMD64_R15_REGNUM /* %r15 */
};
static const int amd64_arch_regmap_len =
(sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0]));
/* Convert architectural register number REG to the appropriate register
number used by GDB. */
static int
amd64_arch_reg_to_regnum (int reg)
{
gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len);
return amd64_arch_regmap[reg];
}
/* Register names for byte pseudo-registers. */
static const char * const amd64_byte_names[] =
{
"al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
"r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
"ah", "bh", "ch", "dh"
};
/* Number of lower byte registers. */
#define AMD64_NUM_LOWER_BYTE_REGS 16
/* Register names for word pseudo-registers. */
static const char * const amd64_word_names[] =
{
"ax", "bx", "cx", "dx", "si", "di", "bp", "",
"r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
};
/* Register names for dword pseudo-registers. */
static const char * const amd64_dword_names[] =
{
"eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
"r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
"eip"
};
/* Return the name of register REGNUM. */
static const char *
amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
if (i386_byte_regnum_p (gdbarch, regnum))
return amd64_byte_names[regnum - tdep->al_regnum];
else if (i386_zmm_regnum_p (gdbarch, regnum))
return amd64_zmm_names[regnum - tdep->zmm0_regnum];
else if (i386_ymm_regnum_p (gdbarch, regnum))
return amd64_ymm_names[regnum - tdep->ymm0_regnum];
else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
return amd64_ymm_avx512_names[regnum - tdep->ymm16_regnum];
else if (i386_word_regnum_p (gdbarch, regnum))
return amd64_word_names[regnum - tdep->ax_regnum];
else if (i386_dword_regnum_p (gdbarch, regnum))
return amd64_dword_names[regnum - tdep->eax_regnum];
else
return i386_pseudo_register_name (gdbarch, regnum);
}
static value *
amd64_pseudo_register_read_value (gdbarch *gdbarch, const frame_info_ptr &next_frame,
int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
if (i386_byte_regnum_p (gdbarch, regnum))
{
int gpnum = regnum - tdep->al_regnum;
/* Extract (always little endian). */
if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
{
gpnum -= AMD64_NUM_LOWER_BYTE_REGS;
/* Special handling for AH, BH, CH, DH. */
return pseudo_from_raw_part (next_frame, regnum, gpnum, 1);
}
else
return pseudo_from_raw_part (next_frame, regnum, gpnum, 0);
}
else if (i386_dword_regnum_p (gdbarch, regnum))
{
int gpnum = regnum - tdep->eax_regnum;
return pseudo_from_raw_part (next_frame, regnum, gpnum, 0);
}
else
return i386_pseudo_register_read_value (gdbarch, next_frame, regnum);
}
static void
amd64_pseudo_register_write (gdbarch *gdbarch, const frame_info_ptr &next_frame,
int regnum, gdb::array_view<const gdb_byte> buf)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
if (i386_byte_regnum_p (gdbarch, regnum))
{
int gpnum = regnum - tdep->al_regnum;
if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
{
gpnum -= AMD64_NUM_LOWER_BYTE_REGS;
pseudo_to_raw_part (next_frame, buf, gpnum, 1);
}
else
pseudo_to_raw_part (next_frame, buf, gpnum, 0);
}
else if (i386_dword_regnum_p (gdbarch, regnum))
{
int gpnum = regnum - tdep->eax_regnum;
pseudo_to_raw_part (next_frame, buf, gpnum, 0);
}
else
i386_pseudo_register_write (gdbarch, next_frame, regnum, buf);
}
/* Implement the 'ax_pseudo_register_collect' gdbarch method. */
static int
amd64_ax_pseudo_register_collect (struct gdbarch *gdbarch,
struct agent_expr *ax, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
if (i386_byte_regnum_p (gdbarch, regnum))
{
int gpnum = regnum - tdep->al_regnum;
if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
ax_reg_mask (ax, gpnum - AMD64_NUM_LOWER_BYTE_REGS);
else
ax_reg_mask (ax, gpnum);
return 0;
}
else if (i386_dword_regnum_p (gdbarch, regnum))
{
int gpnum = regnum - tdep->eax_regnum;
ax_reg_mask (ax, gpnum);
return 0;
}
else
return i386_ax_pseudo_register_collect (gdbarch, ax, regnum);
}
/* Register classes as defined in the psABI. */
enum amd64_reg_class
{
AMD64_INTEGER,
AMD64_SSE,
AMD64_SSEUP,
AMD64_X87,
AMD64_X87UP,
AMD64_COMPLEX_X87,
AMD64_NO_CLASS,
AMD64_MEMORY
};
/* Return the union class of CLASS1 and CLASS2. See the psABI for
details. */
static enum amd64_reg_class
amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
{
/* Rule (a): If both classes are equal, this is the resulting class. */
if (class1 == class2)
return class1;
/* Rule (b): If one of the classes is NO_CLASS, the resulting class
is the other class. */
if (class1 == AMD64_NO_CLASS)
return class2;
if (class2 == AMD64_NO_CLASS)
return class1;
/* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
return AMD64_MEMORY;
/* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
return AMD64_INTEGER;
/* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
MEMORY is used as class. */
if (class1 == AMD64_X87 || class1 == AMD64_X87UP
|| class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
|| class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
return AMD64_MEMORY;
/* Rule (f): Otherwise class SSE is used. */
return AMD64_SSE;
}
static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]);
/* Return true if TYPE is a structure or union with unaligned fields. */
static bool
amd64_has_unaligned_fields (struct type *type)
{
if (type->code () == TYPE_CODE_STRUCT
|| type->code () == TYPE_CODE_UNION)
{
for (int i = 0; i < type->num_fields (); i++)
{
struct type *subtype = check_typedef (type->field (i).type ());
/* Ignore static fields, empty fields (for example nested
empty structures), and bitfields (these are handled by
the caller). */
if (type->field (i).is_static ()
|| (type->field (i).bitsize () == 0
&& subtype->length () == 0)
|| type->field (i).is_packed ())
continue;
int bitpos = type->field (i).loc_bitpos ();
if (bitpos % 8 != 0)
return true;
int align = type_align (subtype);
if (align == 0)
error (_("could not determine alignment of type"));
int bytepos = bitpos / 8;
if (bytepos % align != 0)
return true;
if (amd64_has_unaligned_fields (subtype))
return true;
}
}
return false;
}
/* Classify field I of TYPE starting at BITOFFSET according to the rules for
structures and union types, and store the result in THECLASS. */
static void
amd64_classify_aggregate_field (struct type *type, int i,
enum amd64_reg_class theclass[2],
unsigned int bitoffset)
{
struct type *subtype = check_typedef (type->field (i).type ());
enum amd64_reg_class subclass[2];
int bitsize = type->field (i).bitsize ();
if (bitsize == 0)
bitsize = subtype->length () * 8;
/* Ignore static fields, or empty fields, for example nested
empty structures.*/
if (type->field (i).is_static () || bitsize == 0)
return;
int bitpos = bitoffset + type->field (i).loc_bitpos ();
int pos = bitpos / 64;
int endpos = (bitpos + bitsize - 1) / 64;
if (subtype->code () == TYPE_CODE_STRUCT
|| subtype->code () == TYPE_CODE_UNION)
{
/* Each field of an object is classified recursively. */
int j;
for (j = 0; j < subtype->num_fields (); j++)
amd64_classify_aggregate_field (subtype, j, theclass, bitpos);
return;
}
gdb_assert (pos == 0 || pos == 1);
amd64_classify (subtype, subclass);
theclass[pos] = amd64_merge_classes (theclass[pos], subclass[0]);
if (bitsize <= 64 && pos == 0 && endpos == 1)
/* This is a bit of an odd case: We have a field that would
normally fit in one of the two eightbytes, except that
it is placed in a way that this field straddles them.
This has been seen with a structure containing an array.
The ABI is a bit unclear in this case, but we assume that
this field's class (stored in subclass[0]) must also be merged
into class[1]. In other words, our field has a piece stored
in the second eight-byte, and thus its class applies to
the second eight-byte as well.
In the case where the field length exceeds 8 bytes,
it should not be necessary to merge the field class
into class[1]. As LEN > 8, subclass[1] is necessarily
different from AMD64_NO_CLASS. If subclass[1] is equal
to subclass[0], then the normal class[1]/subclass[1]
merging will take care of everything. For subclass[1]
to be different from subclass[0], I can only see the case
where we have a SSE/SSEUP or X87/X87UP pair, which both
use up all 16 bytes of the aggregate, and are already
handled just fine (because each portion sits on its own
8-byte). */
theclass[1] = amd64_merge_classes (theclass[1], subclass[0]);
if (pos == 0)
theclass[1] = amd64_merge_classes (theclass[1], subclass[1]);
}
/* Classify TYPE according to the rules for aggregate (structures and
arrays) and union types, and store the result in CLASS. */
static void
amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2])
{
/* 1. If the size of an object is larger than two times eight bytes, or
it is a non-trivial C++ object, or it has unaligned fields, then it
has class memory.
It is important that the trivially_copyable check is before the
unaligned fields check, as C++ classes with virtual base classes
will have fields (for the virtual base classes) with non-constant
loc_bitpos attributes, which will cause an assert to trigger within
the unaligned field check. As classes with virtual bases are not
trivially copyable, checking that first avoids this problem. */
if (TYPE_HAS_DYNAMIC_LENGTH (type)
|| type->length () > 16
|| !language_pass_by_reference (type).trivially_copyable
|| amd64_has_unaligned_fields (type))
{
theclass[0] = theclass[1] = AMD64_MEMORY;
return;
}
/* 2. Both eightbytes get initialized to class NO_CLASS. */
theclass[0] = theclass[1] = AMD64_NO_CLASS;
/* 3. Each field of an object is classified recursively so that
always two fields are considered. The resulting class is
calculated according to the classes of the fields in the
eightbyte: */
if (type->code () == TYPE_CODE_ARRAY)
{
struct type *subtype = check_typedef (type->target_type ());
/* All fields in an array have the same type. */
amd64_classify (subtype, theclass);
if (type->length () > 8 && theclass[1] == AMD64_NO_CLASS)
theclass[1] = theclass[0];
}
else
{
int i;
/* Structure or union. */
gdb_assert (type->code () == TYPE_CODE_STRUCT
|| type->code () == TYPE_CODE_UNION);
for (i = 0; i < type->num_fields (); i++)
amd64_classify_aggregate_field (type, i, theclass, 0);
}
/* 4. Then a post merger cleanup is done: */
/* Rule (a): If one of the classes is MEMORY, the whole argument is
passed in memory. */
if (theclass[0] == AMD64_MEMORY || theclass[1] == AMD64_MEMORY)
theclass[0] = theclass[1] = AMD64_MEMORY;
/* Rule (b): If SSEUP is not preceded by SSE, it is converted to
SSE. */
if (theclass[0] == AMD64_SSEUP)
theclass[0] = AMD64_SSE;
if (theclass[1] == AMD64_SSEUP && theclass[0] != AMD64_SSE)
theclass[1] = AMD64_SSE;
}
/* Classify TYPE, and store the result in CLASS. */
static void
amd64_classify (struct type *type, enum amd64_reg_class theclass[2])
{
enum type_code code = type->code ();
int len = type->length ();
theclass[0] = theclass[1] = AMD64_NO_CLASS;
/* Arguments of types (signed and unsigned) _Bool, char, short, int,
long, long long, and pointers are in the INTEGER class. Similarly,
range types, used by languages such as Ada, are also in the INTEGER
class. */
if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
|| code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
|| code == TYPE_CODE_CHAR
|| code == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type))
&& (len == 1 || len == 2 || len == 4 || len == 8))
theclass[0] = AMD64_INTEGER;
/* Arguments of types _Float16, float, double, _Decimal32, _Decimal64 and
__m64 are in class SSE. */
else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
&& (len == 2 || len == 4 || len == 8))
/* FIXME: __m64 . */
theclass[0] = AMD64_SSE;
/* Arguments of types __float128, _Decimal128 and __m128 are split into
two halves. The least significant ones belong to class SSE, the most
significant one to class SSEUP. */
else if (code == TYPE_CODE_DECFLOAT && len == 16)
/* FIXME: __float128, __m128. */
theclass[0] = AMD64_SSE, theclass[1] = AMD64_SSEUP;
/* The 64-bit mantissa of arguments of type long double belongs to
class X87, the 16-bit exponent plus 6 bytes of padding belongs to
class X87UP. */
else if (code == TYPE_CODE_FLT && len == 16)
/* Class X87 and X87UP. */
theclass[0] = AMD64_X87, theclass[1] = AMD64_X87UP;
/* Arguments of complex T - where T is one of the types _Float16, float or
double - get treated as if they are implemented as:
struct complexT {
T real;
T imag;
};
*/
else if (code == TYPE_CODE_COMPLEX && (len == 8 || len == 4))
theclass[0] = AMD64_SSE;
else if (code == TYPE_CODE_COMPLEX && len == 16)
theclass[0] = theclass[1] = AMD64_SSE;
/* A variable of type complex long double is classified as type
COMPLEX_X87. */
else if (code == TYPE_CODE_COMPLEX && len == 32)
theclass[0] = AMD64_COMPLEX_X87;
/* Aggregates. */
else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
|| code == TYPE_CODE_UNION)
amd64_classify_aggregate (type, theclass);
}
static enum return_value_convention
amd64_return_value (struct gdbarch *gdbarch, struct value *function,
struct type *type, struct regcache *regcache,
struct value **read_value, const gdb_byte *writebuf)
{
enum amd64_reg_class theclass[2];
int len = type->length ();
static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
int integer_reg = 0;
int sse_reg = 0;
int i;
gdb_assert (!(read_value && writebuf));
/* 1. Classify the return type with the classification algorithm. */
amd64_classify (type, theclass);
/* 2. If the type has class MEMORY, then the caller provides space
for the return value and passes the address of this storage in
%rdi as if it were the first argument to the function. In effect,
this address becomes a hidden first argument.
On return %rax will contain the address that has been passed in
by the caller in %rdi. */
if (theclass[0] == AMD64_MEMORY)
{
/* As indicated by the comment above, the ABI guarantees that we
can always find the return value just after the function has
returned. */
if (read_value != nullptr)
{
ULONGEST addr;
regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
*read_value = value_at_non_lval (type, addr);
}
return RETURN_VALUE_ABI_RETURNS_ADDRESS;
}
gdb_byte *readbuf = nullptr;
if (read_value != nullptr)
{
*read_value = value::allocate (type);
readbuf = (*read_value)->contents_raw ().data ();
}
/* 8. If the class is COMPLEX_X87, the real part of the value is
returned in %st0 and the imaginary part in %st1. */
if (theclass[0] == AMD64_COMPLEX_X87)
{
if (readbuf)
{
regcache->raw_read (AMD64_ST0_REGNUM, readbuf);
regcache->raw_read (AMD64_ST1_REGNUM, readbuf + 16);
}
if (writebuf)
{
i387_return_value (gdbarch, regcache);
regcache->raw_write (AMD64_ST0_REGNUM, writebuf);
regcache->raw_write (AMD64_ST1_REGNUM, writebuf + 16);
/* Fix up the tag word such that both %st(0) and %st(1) are
marked as valid. */
regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff);
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
gdb_assert (theclass[1] != AMD64_MEMORY);
gdb_assert (len <= 16);
for (i = 0; len > 0; i++, len -= 8)
{
int regnum = -1;
int offset = 0;
switch (theclass[i])
{
case AMD64_INTEGER:
/* 3. If the class is INTEGER, the next available register
of the sequence %rax, %rdx is used. */
regnum = integer_regnum[integer_reg++];
break;
case AMD64_SSE:
/* 4. If the class is SSE, the next available SSE register
of the sequence %xmm0, %xmm1 is used. */
regnum = sse_regnum[sse_reg++];
break;
case AMD64_SSEUP:
/* 5. If the class is SSEUP, the eightbyte is passed in the
upper half of the last used SSE register. */
gdb_assert (sse_reg > 0);
regnum = sse_regnum[sse_reg - 1];
offset = 8;
break;
case AMD64_X87:
/* 6. If the class is X87, the value is returned on the X87
stack in %st0 as 80-bit x87 number. */
regnum = AMD64_ST0_REGNUM;
if (writebuf)
i387_return_value (gdbarch, regcache);
break;
case AMD64_X87UP:
/* 7. If the class is X87UP, the value is returned together
with the previous X87 value in %st0. */
gdb_assert (i > 0 && theclass[0] == AMD64_X87);
regnum = AMD64_ST0_REGNUM;
offset = 8;
len = 2;
break;
case AMD64_NO_CLASS:
continue;
default:
gdb_assert (!"Unexpected register class.");
}
gdb_assert (regnum != -1);
if (readbuf)
regcache->raw_read_part (regnum, offset, std::min (len, 8),
readbuf + i * 8);
if (writebuf)
regcache->raw_write_part (regnum, offset, std::min (len, 8),
writebuf + i * 8);
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
static CORE_ADDR
amd64_push_arguments (struct regcache *regcache, int nargs, struct value **args,
CORE_ADDR sp, function_call_return_method return_method)
{
static int integer_regnum[] =
{
AMD64_RDI_REGNUM, /* %rdi */
AMD64_RSI_REGNUM, /* %rsi */
AMD64_RDX_REGNUM, /* %rdx */
AMD64_RCX_REGNUM, /* %rcx */
AMD64_R8_REGNUM, /* %r8 */
AMD64_R9_REGNUM /* %r9 */
};
static int sse_regnum[] =
{
/* %xmm0 ... %xmm7 */
AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
};
struct value **stack_args = XALLOCAVEC (struct value *, nargs);
int num_stack_args = 0;
int num_elements = 0;
int element = 0;
int integer_reg = 0;
int sse_reg = 0;
int i;
/* Reserve a register for the "hidden" argument. */
if (return_method == return_method_struct)
integer_reg++;
for (i = 0; i < nargs; i++)
{
struct type *type = args[i]->type ();
int len = type->length ();
enum amd64_reg_class theclass[2];
int needed_integer_regs = 0;
int needed_sse_regs = 0;
int j;
/* Classify argument. */
amd64_classify (type, theclass);
/* Calculate the number of integer and SSE registers needed for
this argument. */
for (j = 0; j < 2; j++)
{
if (theclass[j] == AMD64_INTEGER)
needed_integer_regs++;
else if (theclass[j] == AMD64_SSE)
needed_sse_regs++;
}
/* Check whether enough registers are available, and if the
argument should be passed in registers at all. */
if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
|| sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
|| (needed_integer_regs == 0 && needed_sse_regs == 0))
{
/* The argument will be passed on the stack. */
num_elements += ((len + 7) / 8);
stack_args[num_stack_args++] = args[i];
}
else
{
/* The argument will be passed in registers. */
const gdb_byte *valbuf = args[i]->contents ().data ();
gdb_byte buf[8];
gdb_assert (len <= 16);
for (j = 0; len > 0; j++, len -= 8)
{
int regnum = -1;
int offset = 0;
switch (theclass[j])
{
case AMD64_INTEGER:
regnum = integer_regnum[integer_reg++];
break;
case AMD64_SSE:
regnum = sse_regnum[sse_reg++];
break;
case AMD64_SSEUP:
gdb_assert (sse_reg > 0);
regnum = sse_regnum[sse_reg - 1];
offset = 8;
break;
case AMD64_NO_CLASS:
continue;
default:
gdb_assert (!"Unexpected register class.");
}
gdb_assert (regnum != -1);
memset (buf, 0, sizeof buf);
memcpy (buf, valbuf + j * 8, std::min (len, 8));
regcache->raw_write_part (regnum, offset, 8, buf);
}
}
}