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mep-tdep.c
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/* Target-dependent code for the Toshiba MeP for GDB, the GNU debugger.
Copyright (C) 2001-2024 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "extract-store-integer.h"
#include "frame.h"
#include "frame-unwind.h"
#include "frame-base.h"
#include "symtab.h"
#include "gdbtypes.h"
#include "cli/cli-cmds.h"
#include "gdbcore.h"
#include "value.h"
#include "inferior.h"
#include "dis-asm.h"
#include "symfile.h"
#include "objfiles.h"
#include "language.h"
#include "arch-utils.h"
#include "regcache.h"
#include "remote.h"
#include "sim-regno.h"
#include "trad-frame.h"
#include "reggroups.h"
#include "elf-bfd.h"
#include "elf/mep.h"
#include "prologue-value.h"
#include "cgen/bitset.h"
#include "infcall.h"
#include "gdbarch.h"
/* Get the user's customized MeP coprocessor register names from
libopcodes. Make cgen names unique to prevent ODR conflicts with other
targets. */
#define GDB_CGEN_REMAP_PREFIX mep
#include "cgen-remap.h"
#include "opcodes/mep-desc.h"
#include "opcodes/mep-opc.h"
/* The gdbarch_tdep structure. */
/* A quick recap for GDB hackers not familiar with the whole Toshiba
Media Processor story:
The MeP media engine is a configurable processor: users can design
their own coprocessors, implement custom instructions, adjust cache
sizes, select optional standard facilities like add-and-saturate
instructions, and so on. Then, they can build custom versions of
the GNU toolchain to support their customized chips. The
MeP-Integrator program (see utils/mep) takes a GNU toolchain source
tree, and a config file pointing to various files provided by the
user describing their customizations, and edits the source tree to
produce a compiler that can generate their custom instructions, an
assembler that can assemble them and recognize their custom
register names, and so on.
Furthermore, the user can actually specify several of these custom
configurations, called 'me_modules', and get a toolchain which can
produce code for any of them, given a compiler/assembler switch;
you say something like 'gcc -mconfig=mm_max' to generate code for
the me_module named 'mm_max'.
GDB, in particular, needs to:
- use the coprocessor control register names provided by the user
in their hardware description, in expressions, 'info register'
output, and disassembly,
- know the number, names, and types of the coprocessor's
general-purpose registers, adjust the 'info all-registers' output
accordingly, and print error messages if the user refers to one
that doesn't exist
- allow access to the control bus space only when the configuration
actually has a control bus, and recognize which regions of the
control bus space are actually populated,
- disassemble using the user's provided mnemonics for their custom
instructions, and
- recognize whether the $hi and $lo registers are present, and
allow access to them only when they are actually there.
There are three sources of information about what sort of me_module
we're actually dealing with:
- A MeP executable file indicates which me_module it was compiled
for, and libopcodes has tables describing each module. So, given
an executable file, we can find out about the processor it was
compiled for.
- There are SID command-line options to select a particular
me_module, overriding the one specified in the ELF file. SID
provides GDB with a fake read-only register, 'module', which
indicates which me_module GDB is communicating with an instance
of.
- There are SID command-line options to enable or disable certain
optional processor features, overriding the defaults for the
selected me_module. The MeP $OPT register indicates which
options are present on the current processor. */
struct mep_gdbarch_tdep : gdbarch_tdep_base
{
/* A CGEN cpu descriptor for this BFD architecture and machine.
Note: this is *not* customized for any particular me_module; the
MeP libopcodes machinery actually puts off module-specific
customization until the last minute. So this contains
information about all supported me_modules. */
CGEN_CPU_DESC cpu_desc = nullptr;
/* The me_module index from the ELF file we used to select this
architecture, or CONFIG_NONE if there was none.
Note that we should prefer to use the me_module number available
via the 'module' register, whenever we're actually talking to a
real target.
In the absence of live information, we'd like to get the
me_module number from the ELF file. But which ELF file: the
executable file, the core file, ... ? The answer is, "the last
ELF file we used to set the current architecture". Thus, we
create a separate instance of the gdbarch structure for each
me_module value mep_gdbarch_init sees, and store the me_module
value from the ELF file here. */
CONFIG_ATTR me_module {};
};
/* Getting me_module information from the CGEN tables. */
/* Find an entry in the DESC's hardware table whose name begins with
PREFIX, and whose ISA mask intersects COPRO_ISA_MASK, but does not
intersect with GENERIC_ISA_MASK. If there is no matching entry,
return zero. */
static const CGEN_HW_ENTRY *
find_hw_entry_by_prefix_and_isa (CGEN_CPU_DESC desc,
const char *prefix,
CGEN_BITSET *copro_isa_mask,
CGEN_BITSET *generic_isa_mask)
{
int prefix_len = strlen (prefix);
int i;
for (i = 0; i < desc->hw_table.num_entries; i++)
{
const CGEN_HW_ENTRY *hw = desc->hw_table.entries[i];
if (strncmp (prefix, hw->name, prefix_len) == 0)
{
CGEN_BITSET *hw_isa_mask
= ((CGEN_BITSET *)
&CGEN_ATTR_CGEN_HW_ISA_VALUE (CGEN_HW_ATTRS (hw)));
if (cgen_bitset_intersect_p (hw_isa_mask, copro_isa_mask)
&& ! cgen_bitset_intersect_p (hw_isa_mask, generic_isa_mask))
return hw;
}
}
return 0;
}
/* Find an entry in DESC's hardware table whose type is TYPE. Return
zero if there is none. */
static const CGEN_HW_ENTRY *
find_hw_entry_by_type (CGEN_CPU_DESC desc, CGEN_HW_TYPE type)
{
int i;
for (i = 0; i < desc->hw_table.num_entries; i++)
{
const CGEN_HW_ENTRY *hw = desc->hw_table.entries[i];
if (hw->type == type)
return hw;
}
return 0;
}
/* Return the CGEN hardware table entry for the coprocessor register
set for ME_MODULE, whose name prefix is PREFIX. If ME_MODULE has
no such register set, return zero. If ME_MODULE is the generic
me_module CONFIG_NONE, return the table entry for the register set
whose hardware type is GENERIC_TYPE. */
static const CGEN_HW_ENTRY *
me_module_register_set (CONFIG_ATTR me_module,
const char *prefix,
CGEN_HW_TYPE generic_type)
{
/* This is kind of tricky, because the hardware table is constructed
in a way that isn't very helpful. Perhaps we can fix that, but
here's how it works at the moment:
The configuration map, `mep_config_map', is indexed by me_module
number, and indicates which coprocessor and core ISAs that
me_module supports. The 'core_isa' mask includes all the core
ISAs, and the 'cop_isa' mask includes all the coprocessor ISAs.
The entry for the generic me_module, CONFIG_NONE, has an empty
'cop_isa', and its 'core_isa' selects only the standard MeP
instruction set.
The CGEN CPU descriptor's hardware table, desc->hw_table, has
entries for all the register sets, for all me_modules. Each
entry has a mask indicating which ISAs use that register set.
So, if an me_module supports some coprocessor ISA, we can find
applicable register sets by scanning the hardware table for
register sets whose masks include (at least some of) those ISAs.
Each hardware table entry also has a name, whose prefix says
whether it's a general-purpose ("h-cr") or control ("h-ccr")
coprocessor register set. It might be nicer to have an attribute
indicating what sort of register set it was, that we could use
instead of pattern-matching on the name.
When there is no hardware table entry whose mask includes a
particular coprocessor ISA and whose name starts with a given
prefix, then that means that that coprocessor doesn't have any
registers of that type. In such cases, this function must return
a null pointer.
Coprocessor register sets' masks may or may not include the core
ISA for the me_module they belong to. Those generated by a2cgen
do, but the sample me_module included in the unconfigured tree,
'ccfx', does not.
There are generic coprocessor register sets, intended only for
use with the generic me_module. Unfortunately, their masks
include *all* ISAs --- even those for coprocessors that don't
have such register sets. This makes detecting the case where a
coprocessor lacks a particular register set more complicated.
So, here's the approach we take:
- For CONFIG_NONE, we return the generic coprocessor register set.
- For any other me_module, we search for a register set whose
mask contains any of the me_module's coprocessor ISAs,
specifically excluding the generic coprocessor register sets. */
mep_gdbarch_tdep *tdep
= gdbarch_tdep<mep_gdbarch_tdep> (current_inferior ()->arch ());
CGEN_CPU_DESC desc = tdep->cpu_desc;
const CGEN_HW_ENTRY *hw;
if (me_module == CONFIG_NONE)
hw = find_hw_entry_by_type (desc, generic_type);
else
{
CGEN_BITSET *cop = &mep_config_map[me_module].cop_isa;
CGEN_BITSET *core = &mep_config_map[me_module].core_isa;
CGEN_BITSET *generic = &mep_config_map[CONFIG_NONE].core_isa;
CGEN_BITSET *cop_and_core;
/* The coprocessor ISAs include the ISA for the specific core which
has that coprocessor. */
cop_and_core = cgen_bitset_copy (cop);
cgen_bitset_union (cop, core, cop_and_core);
hw = find_hw_entry_by_prefix_and_isa (desc, prefix, cop_and_core, generic);
}
return hw;
}
/* Given a hardware table entry HW representing a register set, return
a pointer to the keyword table with all the register names. If HW
is NULL, return NULL, to propagate the "no such register set" info
along. */
static CGEN_KEYWORD *
register_set_keyword_table (const CGEN_HW_ENTRY *hw)
{
if (! hw)
return NULL;
/* Check that HW is actually a keyword table. */
gdb_assert (hw->asm_type == CGEN_ASM_KEYWORD);
/* The 'asm_data' field of a register set's hardware table entry
refers to a keyword table. */
return (CGEN_KEYWORD *) hw->asm_data;
}
/* Given a keyword table KEYWORD and a register number REGNUM, return
the name of the register, or "" if KEYWORD contains no register
whose number is REGNUM. */
static const char *
register_name_from_keyword (CGEN_KEYWORD *keyword_table, int regnum)
{
const CGEN_KEYWORD_ENTRY *entry
= cgen_keyword_lookup_value (keyword_table, regnum);
if (entry)
{
char *name = entry->name;
/* The CGEN keyword entries for register names include the
leading $, which appears in MeP assembly as well as in GDB.
But we don't want to return that; GDB core code adds that
itself. */
if (name[0] == '$')
name++;
return name;
}
else
return "";
}
/* Masks for option bits in the OPT special-purpose register. */
enum {
MEP_OPT_DIV = 1 << 25, /* 32-bit divide instruction option */
MEP_OPT_MUL = 1 << 24, /* 32-bit multiply instruction option */
MEP_OPT_BIT = 1 << 23, /* bit manipulation instruction option */
MEP_OPT_SAT = 1 << 22, /* saturation instruction option */
MEP_OPT_CLP = 1 << 21, /* clip instruction option */
MEP_OPT_MIN = 1 << 20, /* min/max instruction option */
MEP_OPT_AVE = 1 << 19, /* average instruction option */
MEP_OPT_ABS = 1 << 18, /* absolute difference instruction option */
MEP_OPT_LDZ = 1 << 16, /* leading zero instruction option */
MEP_OPT_VL64 = 1 << 6, /* 64-bit VLIW operation mode option */
MEP_OPT_VL32 = 1 << 5, /* 32-bit VLIW operation mode option */
MEP_OPT_COP = 1 << 4, /* coprocessor option */
MEP_OPT_DSP = 1 << 2, /* DSP option */
MEP_OPT_UCI = 1 << 1, /* UCI option */
MEP_OPT_DBG = 1 << 0, /* DBG function option */
};
/* Given the option_mask value for a particular entry in
mep_config_map, produce the value the processor's OPT register
would use to represent the same set of options. */
static unsigned int
opt_from_option_mask (unsigned int option_mask)
{
/* A table mapping OPT register bits onto CGEN config map option
bits. */
struct {
unsigned int opt_bit, option_mask_bit;
} bits[] = {
{ MEP_OPT_DIV, 1 << CGEN_INSN_OPTIONAL_DIV_INSN },
{ MEP_OPT_MUL, 1 << CGEN_INSN_OPTIONAL_MUL_INSN },
{ MEP_OPT_DIV, 1 << CGEN_INSN_OPTIONAL_DIV_INSN },
{ MEP_OPT_DBG, 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN },
{ MEP_OPT_LDZ, 1 << CGEN_INSN_OPTIONAL_LDZ_INSN },
{ MEP_OPT_ABS, 1 << CGEN_INSN_OPTIONAL_ABS_INSN },
{ MEP_OPT_AVE, 1 << CGEN_INSN_OPTIONAL_AVE_INSN },
{ MEP_OPT_MIN, 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN },
{ MEP_OPT_CLP, 1 << CGEN_INSN_OPTIONAL_CLIP_INSN },
{ MEP_OPT_SAT, 1 << CGEN_INSN_OPTIONAL_SAT_INSN },
{ MEP_OPT_UCI, 1 << CGEN_INSN_OPTIONAL_UCI_INSN },
{ MEP_OPT_DSP, 1 << CGEN_INSN_OPTIONAL_DSP_INSN },
{ MEP_OPT_COP, 1 << CGEN_INSN_OPTIONAL_CP_INSN },
};
int i;
unsigned int opt = 0;
for (i = 0; i < (sizeof (bits) / sizeof (bits[0])); i++)
if (option_mask & bits[i].option_mask_bit)
opt |= bits[i].opt_bit;
return opt;
}
/* Return the value the $OPT register would use to represent the set
of options for ME_MODULE. */
static unsigned int
me_module_opt (CONFIG_ATTR me_module)
{
return opt_from_option_mask (mep_config_map[me_module].option_mask);
}
/* Return the width of ME_MODULE's coprocessor data bus, in bits.
This is either 32 or 64. */
static int
me_module_cop_data_bus_width (CONFIG_ATTR me_module)
{
if (mep_config_map[me_module].option_mask
& (1 << CGEN_INSN_OPTIONAL_CP64_INSN))
return 64;
else
return 32;
}
/* Return true if ME_MODULE is big-endian, false otherwise. */
static int
me_module_big_endian (CONFIG_ATTR me_module)
{
return mep_config_map[me_module].big_endian;
}
/* Return the name of ME_MODULE, or NULL if it has no name. */
static const char *
me_module_name (CONFIG_ATTR me_module)
{
/* The default me_module has "" as its name, but it's easier for our
callers to test for NULL. */
if (! mep_config_map[me_module].name
|| mep_config_map[me_module].name[0] == '\0')
return NULL;
else
return mep_config_map[me_module].name;
}
/* Register set. */
/* The MeP spec defines the following registers:
16 general purpose registers (r0-r15)
32 control/special registers (csr0-csr31)
32 coprocessor general-purpose registers (c0 -- c31)
64 coprocessor control registers (ccr0 -- ccr63)
For the raw registers, we assign numbers here explicitly, instead
of letting the enum assign them for us; the numbers are a matter of
external protocol, and shouldn't shift around as things are edited.
We access the control/special registers via pseudoregisters, to
enforce read-only portions that some registers have.
We access the coprocessor general purpose and control registers via
pseudoregisters, to make sure they appear in the proper order in
the 'info all-registers' command (which uses the register number
ordering), and also to allow them to be renamed and resized
depending on the me_module in use.
The MeP allows coprocessor general-purpose registers to be either
32 or 64 bits long, depending on the configuration. Since we don't
want the format of the 'g' packet to vary from one core to another,
the raw coprocessor GPRs are always 64 bits. GDB doesn't allow the
types of registers to change (see the implementation of
register_type), so we have four banks of pseudoregisters for the
coprocessor gprs --- 32-bit vs. 64-bit, and integer
vs. floating-point --- and we show or hide them depending on the
configuration. */
enum
{
MEP_FIRST_RAW_REGNUM = 0,
MEP_FIRST_GPR_REGNUM = 0,
MEP_R0_REGNUM = 0,
MEP_R1_REGNUM = 1,
MEP_R2_REGNUM = 2,
MEP_R3_REGNUM = 3,
MEP_R4_REGNUM = 4,
MEP_R5_REGNUM = 5,
MEP_R6_REGNUM = 6,
MEP_R7_REGNUM = 7,
MEP_R8_REGNUM = 8,
MEP_R9_REGNUM = 9,
MEP_R10_REGNUM = 10,
MEP_R11_REGNUM = 11,
MEP_R12_REGNUM = 12,
MEP_FP_REGNUM = MEP_R8_REGNUM,
MEP_R13_REGNUM = 13,
MEP_TP_REGNUM = MEP_R13_REGNUM, /* (r13) Tiny data pointer */
MEP_R14_REGNUM = 14,
MEP_GP_REGNUM = MEP_R14_REGNUM, /* (r14) Global pointer */
MEP_R15_REGNUM = 15,
MEP_SP_REGNUM = MEP_R15_REGNUM, /* (r15) Stack pointer */
MEP_LAST_GPR_REGNUM = MEP_R15_REGNUM,
/* The raw control registers. These are the values as received via
the remote protocol, directly from the target; we only let user
code touch the via the pseudoregisters, which enforce read-only
bits. */
MEP_FIRST_RAW_CSR_REGNUM = 16,
MEP_RAW_PC_REGNUM = 16, /* Program counter */
MEP_RAW_LP_REGNUM = 17, /* Link pointer */
MEP_RAW_SAR_REGNUM = 18, /* Raw shift amount */
MEP_RAW_CSR3_REGNUM = 19, /* csr3: reserved */
MEP_RAW_RPB_REGNUM = 20, /* Raw repeat begin address */
MEP_RAW_RPE_REGNUM = 21, /* Repeat end address */
MEP_RAW_RPC_REGNUM = 22, /* Repeat count */
MEP_RAW_HI_REGNUM = 23, /* Upper 32 bits of result of 64 bit mult/div */
MEP_RAW_LO_REGNUM = 24, /* Lower 32 bits of result of 64 bit mult/div */
MEP_RAW_CSR9_REGNUM = 25, /* csr3: reserved */
MEP_RAW_CSR10_REGNUM = 26, /* csr3: reserved */
MEP_RAW_CSR11_REGNUM = 27, /* csr3: reserved */
MEP_RAW_MB0_REGNUM = 28, /* Raw modulo begin address 0 */
MEP_RAW_ME0_REGNUM = 29, /* Raw modulo end address 0 */
MEP_RAW_MB1_REGNUM = 30, /* Raw modulo begin address 1 */
MEP_RAW_ME1_REGNUM = 31, /* Raw modulo end address 1 */
MEP_RAW_PSW_REGNUM = 32, /* Raw program status word */
MEP_RAW_ID_REGNUM = 33, /* Raw processor ID/revision */
MEP_RAW_TMP_REGNUM = 34, /* Temporary */
MEP_RAW_EPC_REGNUM = 35, /* Exception program counter */
MEP_RAW_EXC_REGNUM = 36, /* Raw exception cause */
MEP_RAW_CFG_REGNUM = 37, /* Raw processor configuration*/
MEP_RAW_CSR22_REGNUM = 38, /* csr3: reserved */
MEP_RAW_NPC_REGNUM = 39, /* Nonmaskable interrupt PC */
MEP_RAW_DBG_REGNUM = 40, /* Raw debug */
MEP_RAW_DEPC_REGNUM = 41, /* Debug exception PC */
MEP_RAW_OPT_REGNUM = 42, /* Raw options */
MEP_RAW_RCFG_REGNUM = 43, /* Raw local ram config */
MEP_RAW_CCFG_REGNUM = 44, /* Raw cache config */
MEP_RAW_CSR29_REGNUM = 45, /* csr3: reserved */
MEP_RAW_CSR30_REGNUM = 46, /* csr3: reserved */
MEP_RAW_CSR31_REGNUM = 47, /* csr3: reserved */
MEP_LAST_RAW_CSR_REGNUM = MEP_RAW_CSR31_REGNUM,
/* The raw coprocessor general-purpose registers. These are all 64
bits wide. */
MEP_FIRST_RAW_CR_REGNUM = 48,
MEP_LAST_RAW_CR_REGNUM = MEP_FIRST_RAW_CR_REGNUM + 31,
MEP_FIRST_RAW_CCR_REGNUM = 80,
MEP_LAST_RAW_CCR_REGNUM = MEP_FIRST_RAW_CCR_REGNUM + 63,
/* The module number register. This is the index of the me_module
of which the current target is an instance. (This is not a real
MeP-specified register; it's provided by SID.) */
MEP_MODULE_REGNUM,
MEP_LAST_RAW_REGNUM = MEP_MODULE_REGNUM,
MEP_NUM_RAW_REGS = MEP_LAST_RAW_REGNUM + 1,
/* Pseudoregisters. See mep_pseudo_register_read and
mep_pseudo_register_write. */
MEP_FIRST_PSEUDO_REGNUM = MEP_NUM_RAW_REGS,
/* We have a pseudoregister for every control/special register, to
implement registers with read-only bits. */
MEP_FIRST_CSR_REGNUM = MEP_FIRST_PSEUDO_REGNUM,
MEP_PC_REGNUM = MEP_FIRST_CSR_REGNUM, /* Program counter */
MEP_LP_REGNUM, /* Link pointer */
MEP_SAR_REGNUM, /* shift amount */
MEP_CSR3_REGNUM, /* csr3: reserved */
MEP_RPB_REGNUM, /* repeat begin address */
MEP_RPE_REGNUM, /* Repeat end address */
MEP_RPC_REGNUM, /* Repeat count */
MEP_HI_REGNUM, /* Upper 32 bits of the result of 64 bit mult/div */
MEP_LO_REGNUM, /* Lower 32 bits of the result of 64 bit mult/div */
MEP_CSR9_REGNUM, /* csr3: reserved */
MEP_CSR10_REGNUM, /* csr3: reserved */
MEP_CSR11_REGNUM, /* csr3: reserved */
MEP_MB0_REGNUM, /* modulo begin address 0 */
MEP_ME0_REGNUM, /* modulo end address 0 */
MEP_MB1_REGNUM, /* modulo begin address 1 */
MEP_ME1_REGNUM, /* modulo end address 1 */
MEP_PSW_REGNUM, /* program status word */
MEP_ID_REGNUM, /* processor ID/revision */
MEP_TMP_REGNUM, /* Temporary */
MEP_EPC_REGNUM, /* Exception program counter */
MEP_EXC_REGNUM, /* exception cause */
MEP_CFG_REGNUM, /* processor configuration*/
MEP_CSR22_REGNUM, /* csr3: reserved */
MEP_NPC_REGNUM, /* Nonmaskable interrupt PC */
MEP_DBG_REGNUM, /* debug */
MEP_DEPC_REGNUM, /* Debug exception PC */
MEP_OPT_REGNUM, /* options */
MEP_RCFG_REGNUM, /* local ram config */
MEP_CCFG_REGNUM, /* cache config */
MEP_CSR29_REGNUM, /* csr3: reserved */
MEP_CSR30_REGNUM, /* csr3: reserved */
MEP_CSR31_REGNUM, /* csr3: reserved */
MEP_LAST_CSR_REGNUM = MEP_CSR31_REGNUM,
/* The 32-bit integer view of the coprocessor GPR's. */
MEP_FIRST_CR32_REGNUM,
MEP_LAST_CR32_REGNUM = MEP_FIRST_CR32_REGNUM + 31,
/* The 32-bit floating-point view of the coprocessor GPR's. */
MEP_FIRST_FP_CR32_REGNUM,
MEP_LAST_FP_CR32_REGNUM = MEP_FIRST_FP_CR32_REGNUM + 31,
/* The 64-bit integer view of the coprocessor GPR's. */
MEP_FIRST_CR64_REGNUM,
MEP_LAST_CR64_REGNUM = MEP_FIRST_CR64_REGNUM + 31,
/* The 64-bit floating-point view of the coprocessor GPR's. */
MEP_FIRST_FP_CR64_REGNUM,
MEP_LAST_FP_CR64_REGNUM = MEP_FIRST_FP_CR64_REGNUM + 31,
MEP_FIRST_CCR_REGNUM,
MEP_LAST_CCR_REGNUM = MEP_FIRST_CCR_REGNUM + 63,
MEP_LAST_PSEUDO_REGNUM = MEP_LAST_CCR_REGNUM,
MEP_NUM_PSEUDO_REGS = (MEP_LAST_PSEUDO_REGNUM - MEP_LAST_RAW_REGNUM),
MEP_NUM_REGS = MEP_NUM_RAW_REGS + MEP_NUM_PSEUDO_REGS
};
#define IN_SET(set, n) \
(MEP_FIRST_ ## set ## _REGNUM <= (n) && (n) <= MEP_LAST_ ## set ## _REGNUM)
#define IS_GPR_REGNUM(n) (IN_SET (GPR, (n)))
#define IS_RAW_CSR_REGNUM(n) (IN_SET (RAW_CSR, (n)))
#define IS_RAW_CR_REGNUM(n) (IN_SET (RAW_CR, (n)))
#define IS_RAW_CCR_REGNUM(n) (IN_SET (RAW_CCR, (n)))
#define IS_CSR_REGNUM(n) (IN_SET (CSR, (n)))
#define IS_CR32_REGNUM(n) (IN_SET (CR32, (n)))
#define IS_FP_CR32_REGNUM(n) (IN_SET (FP_CR32, (n)))
#define IS_CR64_REGNUM(n) (IN_SET (CR64, (n)))
#define IS_FP_CR64_REGNUM(n) (IN_SET (FP_CR64, (n)))
#define IS_CR_REGNUM(n) (IS_CR32_REGNUM (n) || IS_FP_CR32_REGNUM (n) \
|| IS_CR64_REGNUM (n) || IS_FP_CR64_REGNUM (n))
#define IS_CCR_REGNUM(n) (IN_SET (CCR, (n)))
#define IS_RAW_REGNUM(n) (IN_SET (RAW, (n)))
#define IS_PSEUDO_REGNUM(n) (IN_SET (PSEUDO, (n)))
#define NUM_REGS_IN_SET(set) \
(MEP_LAST_ ## set ## _REGNUM - MEP_FIRST_ ## set ## _REGNUM + 1)
#define MEP_GPR_SIZE (4) /* Size of a MeP general-purpose register. */
#define MEP_PSW_SIZE (4) /* Size of the PSW register. */
#define MEP_LP_SIZE (4) /* Size of the LP register. */
/* Many of the control/special registers contain bits that cannot be
written to; some are entirely read-only. So we present them all as
pseudoregisters.
The following table describes the special properties of each CSR. */
struct mep_csr_register
{
/* The number of this CSR's raw register. */
int raw;
/* The number of this CSR's pseudoregister. */
int pseudo;
/* A mask of the bits that are writeable: if a bit is set here, then
it can be modified; if the bit is clear, then it cannot. */
LONGEST writeable_bits;
};
/* mep_csr_registers[i] describes the i'th CSR.
We just list the register numbers here explicitly to help catch
typos. */
#define CSR(name) MEP_RAW_ ## name ## _REGNUM, MEP_ ## name ## _REGNUM
static mep_csr_register mep_csr_registers[] = {
{ CSR(PC), 0xffffffff }, /* manual says r/o, but we can write it */
{ CSR(LP), 0xffffffff },
{ CSR(SAR), 0x0000003f },
{ CSR(CSR3), 0xffffffff },
{ CSR(RPB), 0xfffffffe },
{ CSR(RPE), 0xffffffff },
{ CSR(RPC), 0xffffffff },
{ CSR(HI), 0xffffffff },
{ CSR(LO), 0xffffffff },
{ CSR(CSR9), 0xffffffff },
{ CSR(CSR10), 0xffffffff },
{ CSR(CSR11), 0xffffffff },
{ CSR(MB0), 0x0000ffff },
{ CSR(ME0), 0x0000ffff },
{ CSR(MB1), 0x0000ffff },
{ CSR(ME1), 0x0000ffff },
{ CSR(PSW), 0x000003ff },
{ CSR(ID), 0x00000000 },
{ CSR(TMP), 0xffffffff },
{ CSR(EPC), 0xffffffff },
{ CSR(EXC), 0x000030f0 },
{ CSR(CFG), 0x00c0001b },
{ CSR(CSR22), 0xffffffff },
{ CSR(NPC), 0xffffffff },
{ CSR(DBG), 0x00000580 },
{ CSR(DEPC), 0xffffffff },
{ CSR(OPT), 0x00000000 },
{ CSR(RCFG), 0x00000000 },
{ CSR(CCFG), 0x00000000 },
{ CSR(CSR29), 0xffffffff },
{ CSR(CSR30), 0xffffffff },
{ CSR(CSR31), 0xffffffff },
};
/* If R is the number of a raw register, then mep_raw_to_pseudo[R] is
the number of the corresponding pseudoregister. Otherwise,
mep_raw_to_pseudo[R] == R. */
static int mep_raw_to_pseudo[MEP_NUM_REGS];
/* If R is the number of a pseudoregister, then mep_pseudo_to_raw[R]
is the number of the underlying raw register. Otherwise
mep_pseudo_to_raw[R] == R. */
static int mep_pseudo_to_raw[MEP_NUM_REGS];
static void
mep_init_pseudoregister_maps (void)
{
int i;
/* Verify that mep_csr_registers covers all the CSRs, in order. */
gdb_assert (ARRAY_SIZE (mep_csr_registers) == NUM_REGS_IN_SET (CSR));
gdb_assert (ARRAY_SIZE (mep_csr_registers) == NUM_REGS_IN_SET (RAW_CSR));
/* Verify that the raw and pseudo ranges have matching sizes. */
gdb_assert (NUM_REGS_IN_SET (RAW_CSR) == NUM_REGS_IN_SET (CSR));
gdb_assert (NUM_REGS_IN_SET (RAW_CR) == NUM_REGS_IN_SET (CR32));
gdb_assert (NUM_REGS_IN_SET (RAW_CR) == NUM_REGS_IN_SET (CR64));
gdb_assert (NUM_REGS_IN_SET (RAW_CCR) == NUM_REGS_IN_SET (CCR));
for (i = 0; i < ARRAY_SIZE (mep_csr_registers); i++)
{
struct mep_csr_register *r = &mep_csr_registers[i];
gdb_assert (r->pseudo == MEP_FIRST_CSR_REGNUM + i);
gdb_assert (r->raw == MEP_FIRST_RAW_CSR_REGNUM + i);
}
/* Set up the initial raw<->pseudo mappings. */
for (i = 0; i < MEP_NUM_REGS; i++)
{
mep_raw_to_pseudo[i] = i;
mep_pseudo_to_raw[i] = i;
}
/* Add the CSR raw<->pseudo mappings. */
for (i = 0; i < ARRAY_SIZE (mep_csr_registers); i++)
{
struct mep_csr_register *r = &mep_csr_registers[i];
mep_raw_to_pseudo[r->raw] = r->pseudo;
mep_pseudo_to_raw[r->pseudo] = r->raw;
}
/* Add the CR raw<->pseudo mappings. */
for (i = 0; i < NUM_REGS_IN_SET (RAW_CR); i++)
{
int raw = MEP_FIRST_RAW_CR_REGNUM + i;
int pseudo32 = MEP_FIRST_CR32_REGNUM + i;
int pseudofp32 = MEP_FIRST_FP_CR32_REGNUM + i;
int pseudo64 = MEP_FIRST_CR64_REGNUM + i;
int pseudofp64 = MEP_FIRST_FP_CR64_REGNUM + i;
/* Truly, the raw->pseudo mapping depends on the current module.
But we use the raw->pseudo mapping when we read the debugging
info; at that point, we don't know what module we'll actually
be running yet. So, we always supply the 64-bit register
numbers; GDB knows how to pick a smaller value out of a
larger register properly. */
mep_raw_to_pseudo[raw] = pseudo64;
mep_pseudo_to_raw[pseudo32] = raw;
mep_pseudo_to_raw[pseudofp32] = raw;
mep_pseudo_to_raw[pseudo64] = raw;
mep_pseudo_to_raw[pseudofp64] = raw;
}
/* Add the CCR raw<->pseudo mappings. */
for (i = 0; i < NUM_REGS_IN_SET (CCR); i++)
{
int raw = MEP_FIRST_RAW_CCR_REGNUM + i;
int pseudo = MEP_FIRST_CCR_REGNUM + i;
mep_raw_to_pseudo[raw] = pseudo;
mep_pseudo_to_raw[pseudo] = raw;
}
}
static int
mep_debug_reg_to_regnum (struct gdbarch *gdbarch, int debug_reg)
{
/* The debug info uses the raw register numbers. */
if (debug_reg >= 0 && debug_reg < ARRAY_SIZE (mep_raw_to_pseudo))
return mep_raw_to_pseudo[debug_reg];
return -1;
}
/* Return the size, in bits, of the coprocessor pseudoregister
numbered PSEUDO. */
static int
mep_pseudo_cr_size (int pseudo)
{
if (IS_CR32_REGNUM (pseudo)
|| IS_FP_CR32_REGNUM (pseudo))
return 32;
else if (IS_CR64_REGNUM (pseudo)
|| IS_FP_CR64_REGNUM (pseudo))
return 64;
else
gdb_assert_not_reached ("unexpected coprocessor pseudo register");
}
/* If the coprocessor pseudoregister numbered PSEUDO is a
floating-point register, return non-zero; if it is an integer
register, return zero. */
static int
mep_pseudo_cr_is_float (int pseudo)
{
return (IS_FP_CR32_REGNUM (pseudo)
|| IS_FP_CR64_REGNUM (pseudo));
}
/* Given a coprocessor GPR pseudoregister number, return its index
within that register bank. */
static int
mep_pseudo_cr_index (int pseudo)
{
if (IS_CR32_REGNUM (pseudo))
return pseudo - MEP_FIRST_CR32_REGNUM;
else if (IS_FP_CR32_REGNUM (pseudo))
return pseudo - MEP_FIRST_FP_CR32_REGNUM;
else if (IS_CR64_REGNUM (pseudo))
return pseudo - MEP_FIRST_CR64_REGNUM;
else if (IS_FP_CR64_REGNUM (pseudo))
return pseudo - MEP_FIRST_FP_CR64_REGNUM;
else
gdb_assert_not_reached ("unexpected coprocessor pseudo register");
}
/* Return the me_module index describing the current target.
If the current target has registers (e.g., simulator, remote
target), then this uses the value of the 'module' register, raw
register MEP_MODULE_REGNUM. Otherwise, this retrieves the value
from the ELF header's e_flags field of the current executable
file. */
static CONFIG_ATTR
current_me_module (void)
{
if (target_has_registers ())
{
ULONGEST regval;
regcache_cooked_read_unsigned (get_thread_regcache (inferior_thread ()),
MEP_MODULE_REGNUM, ®val);
return (CONFIG_ATTR) regval;
}
else
{
mep_gdbarch_tdep *tdep
= gdbarch_tdep<mep_gdbarch_tdep> (current_inferior ()->arch ());
return tdep->me_module;
}
}
/* Return the set of options for the current target, in the form that
the OPT register would use.
If the current target has registers (e.g., simulator, remote
target), then this is the actual value of the OPT register. If the
current target does not have registers (e.g., an executable file),
then use the 'module_opt' field we computed when we build the
gdbarch object for this module. */
static unsigned int
current_options (void)
{
if (target_has_registers ())
{
ULONGEST regval;
regcache_cooked_read_unsigned (get_thread_regcache (inferior_thread ()),
MEP_OPT_REGNUM, ®val);
return regval;
}
else
return me_module_opt (current_me_module ());
}
/* Return the width of the current me_module's coprocessor data bus,
in bits. This is either 32 or 64. */
static int
current_cop_data_bus_width (void)
{
return me_module_cop_data_bus_width (current_me_module ());
}
/* Return the keyword table of coprocessor general-purpose register
names appropriate for the me_module we're dealing with. */
static CGEN_KEYWORD *
current_cr_names (void)
{
const CGEN_HW_ENTRY *hw
= me_module_register_set (current_me_module (), "h-cr-", HW_H_CR);
return register_set_keyword_table (hw);
}
/* Return non-zero if the coprocessor general-purpose registers are
floating-point values, zero otherwise. */
static int
current_cr_is_float (void)
{
const CGEN_HW_ENTRY *hw
= me_module_register_set (current_me_module (), "h-cr-", HW_H_CR);
return CGEN_ATTR_CGEN_HW_IS_FLOAT_VALUE (CGEN_HW_ATTRS (hw));
}
/* Return the keyword table of coprocessor control register names
appropriate for the me_module we're dealing with. */
static CGEN_KEYWORD *
current_ccr_names (void)
{
const CGEN_HW_ENTRY *hw
= me_module_register_set (current_me_module (), "h-ccr-", HW_H_CCR);
return register_set_keyword_table (hw);
}
static const char *
mep_register_name (struct gdbarch *gdbarch, int regnr)
{
/* General-purpose registers. */
static const char *gpr_names[] = {
"r0", "r1", "r2", "r3", /* 0 */
"r4", "r5", "r6", "r7", /* 4 */
"fp", "r9", "r10", "r11", /* 8 */
"r12", "tp", "gp", "sp" /* 12 */
};
/* Special-purpose registers. */
static const char *csr_names[] = {
"pc", "lp", "sar", "", /* 0 csr3: reserved */
"rpb", "rpe", "rpc", "hi", /* 4 */
"lo", "", "", "", /* 8 csr9-csr11: reserved */
"mb0", "me0", "mb1", "me1", /* 12 */
"psw", "id", "tmp", "epc", /* 16 */
"exc", "cfg", "", "npc", /* 20 csr22: reserved */
"dbg", "depc", "opt", "rcfg", /* 24 */
"ccfg", "", "", "" /* 28 csr29-csr31: reserved */
};
if (IS_GPR_REGNUM (regnr))
return gpr_names[regnr - MEP_R0_REGNUM];
else if (IS_CSR_REGNUM (regnr))
{
/* The 'hi' and 'lo' registers are only present on processors
that have the 'MUL' or 'DIV' instructions enabled. */
if ((regnr == MEP_HI_REGNUM || regnr == MEP_LO_REGNUM)
&& (! (current_options () & (MEP_OPT_MUL | MEP_OPT_DIV))))
return "";
return csr_names[regnr - MEP_FIRST_CSR_REGNUM];
}
else if (IS_CR_REGNUM (regnr))
{
CGEN_KEYWORD *names;
int cr_size;
int cr_is_float;
/* Does this module have a coprocessor at all? */
if (! (current_options () & MEP_OPT_COP))
return "";
names = current_cr_names ();
if (! names)
/* This module's coprocessor has no general-purpose registers. */
return "";
cr_size = current_cop_data_bus_width ();
if (cr_size != mep_pseudo_cr_size (regnr))
/* This module's coprocessor's GPR's are of a different size. */
return "";
cr_is_float = current_cr_is_float ();
/* The extra ! operators ensure we get boolean equality, not
numeric equality. */
if (! cr_is_float != ! mep_pseudo_cr_is_float (regnr))
/* This module's coprocessor's GPR's are of a different type. */
return "";
return register_name_from_keyword (names, mep_pseudo_cr_index (regnr));
}