forked from bminor/binutils-gdb
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathsim-main.c
1611 lines (1502 loc) · 51.3 KB
/
sim-main.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/* RISC-V simulator.
Copyright (C) 2005-2024 Free Software Foundation, Inc.
Contributed by Mike Frysinger.
This file is part of simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* This file contains the main simulator decoding logic. i.e. everything that
is architecture specific. */
/* This must come before any other includes. */
#include "defs.h"
#include <inttypes.h>
#include <time.h>
#include "sim-main.h"
#include "sim-signal.h"
#include "sim-syscall.h"
#include "opcode/riscv.h"
#include "sim/sim-riscv.h"
#include "riscv-sim.h"
#define TRACE_REG(cpu, reg) \
TRACE_REGISTER (cpu, "wrote %s = %#" PRIxTW, riscv_gpr_names_abi[reg], \
RISCV_SIM_CPU (cpu)->regs[reg])
static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : 0x7f))
#define RISCV_ASSERT_RV32(cpu, fmt, args...) \
do { \
if (RISCV_XLEN (cpu) != 32) \
{ \
TRACE_INSN (cpu, "RV32I-only " fmt, ## args); \
sim_engine_halt (CPU_STATE (cpu), cpu, NULL, sim_pc_get (cpu), \
sim_signalled, SIM_SIGILL); \
} \
} while (0)
#define RISCV_ASSERT_RV64(cpu, fmt, args...) \
do { \
if (RISCV_XLEN (cpu) != 64) \
{ \
TRACE_INSN (cpu, "RV64I-only " fmt, ## args); \
sim_engine_halt (CPU_STATE (cpu), cpu, NULL, sim_pc_get (cpu), \
sim_signalled, SIM_SIGILL); \
} \
} while (0)
static INLINE void
store_rd (SIM_CPU *cpu, int rd, unsigned_word val)
{
struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
if (rd)
{
riscv_cpu->regs[rd] = val;
TRACE_REG (cpu, rd);
}
}
static INLINE unsigned_word
fetch_csr (SIM_CPU *cpu, const char *name, int csr, unsigned_word *reg)
{
/* Handle pseudo registers. */
switch (csr)
{
/* Allow certain registers only in respective modes. */
case CSR_CYCLEH:
case CSR_INSTRETH:
case CSR_TIMEH:
RISCV_ASSERT_RV32 (cpu, "CSR: %s", name);
break;
}
return *reg;
}
static INLINE void
store_csr (SIM_CPU *cpu, const char *name, int csr, unsigned_word *reg,
unsigned_word val)
{
struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
switch (csr)
{
/* These are pseudo registers that modify sub-fields of fcsr. */
case CSR_FRM:
val &= 0x7;
*reg = val;
riscv_cpu->csr.fcsr = (riscv_cpu->csr.fcsr & ~0xe0) | (val << 5);
break;
case CSR_FFLAGS:
val &= 0x1f;
*reg = val;
riscv_cpu->csr.fcsr = (riscv_cpu->csr.fcsr & ~0x1f) | val;
break;
/* Keep the sub-fields in sync. */
case CSR_FCSR:
*reg = val;
riscv_cpu->csr.frm = (val >> 5) & 0x7;
riscv_cpu->csr.fflags = val & 0x1f;
break;
/* Allow certain registers only in respective modes. */
case CSR_CYCLEH:
case CSR_INSTRETH:
case CSR_TIMEH:
RISCV_ASSERT_RV32 (cpu, "CSR: %s", name);
ATTRIBUTE_FALLTHROUGH;
/* All the rest are immutable. */
default:
val = *reg;
break;
}
TRACE_REGISTER (cpu, "wrote CSR %s = %#" PRIxTW, name, val);
}
static inline unsigned_word
ashiftrt (unsigned_word val, unsigned_word shift)
{
uint32_t sign = (val & 0x80000000) ? ~(0xfffffffful >> shift) : 0;
return (val >> shift) | sign;
}
static inline unsigned_word
ashiftrt64 (unsigned_word val, unsigned_word shift)
{
uint64_t sign =
(val & 0x8000000000000000ull) ? ~(0xffffffffffffffffull >> shift) : 0;
return (val >> shift) | sign;
}
static sim_cia
execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
{
SIM_DESC sd = CPU_STATE (cpu);
struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
int rs2 = (iw >> OP_SH_RS2) & OP_MASK_RS2;
const char *rd_name = riscv_gpr_names_abi[rd];
const char *rs1_name = riscv_gpr_names_abi[rs1];
const char *rs2_name = riscv_gpr_names_abi[rs2];
unsigned int csr = (iw >> OP_SH_CSR) & OP_MASK_CSR;
unsigned_word i_imm = EXTRACT_ITYPE_IMM (iw);
unsigned_word u_imm = EXTRACT_UTYPE_IMM ((uint64_t) iw);
unsigned_word s_imm = EXTRACT_STYPE_IMM (iw);
unsigned_word sb_imm = EXTRACT_BTYPE_IMM (iw);
unsigned_word shamt_imm = ((iw >> OP_SH_SHAMT) & OP_MASK_SHAMT);
unsigned_word tmp;
sim_cia pc = riscv_cpu->pc + 4;
TRACE_EXTRACT (cpu,
"rd:%-2i:%-4s "
"rs1:%-2i:%-4s %0*" PRIxTW " "
"rs2:%-2i:%-4s %0*" PRIxTW " "
"match:%#x mask:%#x",
rd, rd_name,
rs1, rs1_name, (int) sizeof (unsigned_word) * 2,
riscv_cpu->regs[rs1],
rs2, rs2_name, (int) sizeof (unsigned_word) * 2,
riscv_cpu->regs[rs2],
(unsigned) op->match, (unsigned) op->mask);
switch (op->match)
{
case MATCH_ADD:
TRACE_INSN (cpu, "add %s, %s, %s; // %s = %s + %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
store_rd (cpu, rd, riscv_cpu->regs[rs1] + riscv_cpu->regs[rs2]);
break;
case MATCH_ADDW:
TRACE_INSN (cpu, "addw %s, %s, %s; // %s = %s + %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd,
EXTEND32 (riscv_cpu->regs[rs1] + riscv_cpu->regs[rs2]));
break;
case MATCH_ADDI:
TRACE_INSN (cpu, "addi %s, %s, %#" PRIxTW "; // %s = %s + %#" PRIxTW,
rd_name, rs1_name, i_imm, rd_name, rs1_name, i_imm);
store_rd (cpu, rd, riscv_cpu->regs[rs1] + i_imm);
break;
case MATCH_ADDIW:
TRACE_INSN (cpu, "addiw %s, %s, %#" PRIxTW "; // %s = %s + %#" PRIxTW,
rd_name, rs1_name, i_imm, rd_name, rs1_name, i_imm);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd, EXTEND32 (riscv_cpu->regs[rs1] + i_imm));
break;
case MATCH_AND:
TRACE_INSN (cpu, "and %s, %s, %s; // %s = %s & %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
store_rd (cpu, rd, riscv_cpu->regs[rs1] & riscv_cpu->regs[rs2]);
break;
case MATCH_ANDI:
TRACE_INSN (cpu, "andi %s, %s, %" PRIiTW "; // %s = %s & %#" PRIxTW,
rd_name, rs1_name, i_imm, rd_name, rs1_name, i_imm);
store_rd (cpu, rd, riscv_cpu->regs[rs1] & i_imm);
break;
case MATCH_OR:
TRACE_INSN (cpu, "or %s, %s, %s; // %s = %s | %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
store_rd (cpu, rd, riscv_cpu->regs[rs1] | riscv_cpu->regs[rs2]);
break;
case MATCH_ORI:
TRACE_INSN (cpu, "ori %s, %s, %" PRIiTW "; // %s = %s | %#" PRIxTW,
rd_name, rs1_name, i_imm, rd_name, rs1_name, i_imm);
store_rd (cpu, rd, riscv_cpu->regs[rs1] | i_imm);
break;
case MATCH_XOR:
TRACE_INSN (cpu, "xor %s, %s, %s; // %s = %s ^ %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
store_rd (cpu, rd, riscv_cpu->regs[rs1] ^ riscv_cpu->regs[rs2]);
break;
case MATCH_XORI:
TRACE_INSN (cpu, "xori %s, %s, %" PRIiTW "; // %s = %s ^ %#" PRIxTW,
rd_name, rs1_name, i_imm, rd_name, rs1_name, i_imm);
store_rd (cpu, rd, riscv_cpu->regs[rs1] ^ i_imm);
break;
case MATCH_SUB:
TRACE_INSN (cpu, "sub %s, %s, %s; // %s = %s - %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
store_rd (cpu, rd, riscv_cpu->regs[rs1] - riscv_cpu->regs[rs2]);
break;
case MATCH_SUBW:
TRACE_INSN (cpu, "subw %s, %s, %s; // %s = %s - %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd,
EXTEND32 (riscv_cpu->regs[rs1] - riscv_cpu->regs[rs2]));
break;
case MATCH_LUI:
TRACE_INSN (cpu, "lui %s, %#" PRIxTW ";", rd_name, u_imm);
store_rd (cpu, rd, u_imm);
break;
case MATCH_SLL:
TRACE_INSN (cpu, "sll %s, %s, %s; // %s = %s << %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
u_imm = RISCV_XLEN (cpu) == 32 ? 0x1f : 0x3f;
store_rd (cpu, rd,
riscv_cpu->regs[rs1] << (riscv_cpu->regs[rs2] & u_imm));
break;
case MATCH_SLLW:
TRACE_INSN (cpu, "sllw %s, %s, %s; // %s = %s << %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd, EXTEND32 (
(uint32_t) riscv_cpu->regs[rs1] << (riscv_cpu->regs[rs2] & 0x1f)));
break;
case MATCH_SLLI:
TRACE_INSN (cpu, "slli %s, %s, %" PRIiTW "; // %s = %s << %#" PRIxTW,
rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
if (RISCV_XLEN (cpu) == 32 && shamt_imm > 0x1f)
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
SIM_SIGILL);
store_rd (cpu, rd, riscv_cpu->regs[rs1] << shamt_imm);
break;
case MATCH_SLLIW:
TRACE_INSN (cpu, "slliw %s, %s, %" PRIiTW "; // %s = %s << %#" PRIxTW,
rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd,
EXTEND32 ((uint32_t) riscv_cpu->regs[rs1] << shamt_imm));
break;
case MATCH_SRL:
TRACE_INSN (cpu, "srl %s, %s, %s; // %s = %s >> %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
u_imm = RISCV_XLEN (cpu) == 32 ? 0x1f : 0x3f;
store_rd (cpu, rd,
riscv_cpu->regs[rs1] >> (riscv_cpu->regs[rs2] & u_imm));
break;
case MATCH_SRLW:
TRACE_INSN (cpu, "srlw %s, %s, %s; // %s = %s >> %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd, EXTEND32 (
(uint32_t) riscv_cpu->regs[rs1] >> (riscv_cpu->regs[rs2] & 0x1f)));
break;
case MATCH_SRLI:
TRACE_INSN (cpu, "srli %s, %s, %" PRIiTW "; // %s = %s >> %#" PRIxTW,
rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
if (RISCV_XLEN (cpu) == 32 && shamt_imm > 0x1f)
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
SIM_SIGILL);
store_rd (cpu, rd, riscv_cpu->regs[rs1] >> shamt_imm);
break;
case MATCH_SRLIW:
TRACE_INSN (cpu, "srliw %s, %s, %" PRIiTW "; // %s = %s >> %#" PRIxTW,
rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd,
EXTEND32 ((uint32_t) riscv_cpu->regs[rs1] >> shamt_imm));
break;
case MATCH_SRA:
TRACE_INSN (cpu, "sra %s, %s, %s; // %s = %s >>> %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
if (RISCV_XLEN (cpu) == 32)
tmp = ashiftrt (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2] & 0x1f);
else
tmp = ashiftrt64 (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2] & 0x3f);
store_rd (cpu, rd, tmp);
break;
case MATCH_SRAW:
TRACE_INSN (cpu, "sraw %s, %s, %s; // %s = %s >>> %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd, EXTEND32 (
ashiftrt ((int32_t) riscv_cpu->regs[rs1],
riscv_cpu->regs[rs2] & 0x1f)));
break;
case MATCH_SRAI:
TRACE_INSN (cpu, "srai %s, %s, %" PRIiTW "; // %s = %s >>> %#" PRIxTW,
rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
if (RISCV_XLEN (cpu) == 32)
{
if (shamt_imm > 0x1f)
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
SIM_SIGILL);
tmp = ashiftrt (riscv_cpu->regs[rs1], shamt_imm);
}
else
tmp = ashiftrt64 (riscv_cpu->regs[rs1], shamt_imm);
store_rd (cpu, rd, tmp);
break;
case MATCH_SRAIW:
TRACE_INSN (cpu, "sraiw %s, %s, %" PRIiTW "; // %s = %s >>> %#" PRIxTW,
rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd, EXTEND32 (
ashiftrt ((int32_t) riscv_cpu->regs[rs1], shamt_imm)));
break;
case MATCH_SLT:
TRACE_INSN (cpu, "slt");
store_rd (cpu, rd,
!!((signed_word) riscv_cpu->regs[rs1] <
(signed_word) riscv_cpu->regs[rs2]));
break;
case MATCH_SLTU:
TRACE_INSN (cpu, "sltu");
store_rd (cpu, rd, !!((unsigned_word) riscv_cpu->regs[rs1] <
(unsigned_word) riscv_cpu->regs[rs2]));
break;
case MATCH_SLTI:
TRACE_INSN (cpu, "slti");
store_rd (cpu, rd, !!((signed_word) riscv_cpu->regs[rs1] <
(signed_word) i_imm));
break;
case MATCH_SLTIU:
TRACE_INSN (cpu, "sltiu");
store_rd (cpu, rd, !!((unsigned_word) riscv_cpu->regs[rs1] <
(unsigned_word) i_imm));
break;
case MATCH_AUIPC:
TRACE_INSN (cpu, "auipc %s, %" PRIiTW "; // %s = pc + %" PRIiTW,
rd_name, u_imm, rd_name, u_imm);
store_rd (cpu, rd, riscv_cpu->pc + u_imm);
break;
case MATCH_BEQ:
TRACE_INSN (cpu, "beq %s, %s, %#" PRIxTW "; "
"// if (%s == %s) goto %#" PRIxTW,
rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, sb_imm);
if (riscv_cpu->regs[rs1] == riscv_cpu->regs[rs2])
{
pc = riscv_cpu->pc + sb_imm;
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
}
break;
case MATCH_BLT:
TRACE_INSN (cpu, "blt %s, %s, %#" PRIxTW "; "
"// if (%s < %s) goto %#" PRIxTW,
rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, sb_imm);
if ((signed_word) riscv_cpu->regs[rs1] <
(signed_word) riscv_cpu->regs[rs2])
{
pc = riscv_cpu->pc + sb_imm;
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
}
break;
case MATCH_BLTU:
TRACE_INSN (cpu, "bltu %s, %s, %#" PRIxTW "; "
"// if (%s < %s) goto %#" PRIxTW,
rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, sb_imm);
if ((unsigned_word) riscv_cpu->regs[rs1] <
(unsigned_word) riscv_cpu->regs[rs2])
{
pc = riscv_cpu->pc + sb_imm;
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
}
break;
case MATCH_BGE:
TRACE_INSN (cpu, "bge %s, %s, %#" PRIxTW "; "
"// if (%s >= %s) goto %#" PRIxTW,
rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, sb_imm);
if ((signed_word) riscv_cpu->regs[rs1] >=
(signed_word) riscv_cpu->regs[rs2])
{
pc = riscv_cpu->pc + sb_imm;
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
}
break;
case MATCH_BGEU:
TRACE_INSN (cpu, "bgeu %s, %s, %#" PRIxTW "; "
"// if (%s >= %s) goto %#" PRIxTW,
rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, sb_imm);
if ((unsigned_word) riscv_cpu->regs[rs1] >=
(unsigned_word) riscv_cpu->regs[rs2])
{
pc = riscv_cpu->pc + sb_imm;
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
}
break;
case MATCH_BNE:
TRACE_INSN (cpu, "bne %s, %s, %#" PRIxTW "; "
"// if (%s != %s) goto %#" PRIxTW,
rs1_name, rs2_name, sb_imm, rs1_name, rs2_name, sb_imm);
if (riscv_cpu->regs[rs1] != riscv_cpu->regs[rs2])
{
pc = riscv_cpu->pc + sb_imm;
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
}
break;
case MATCH_JAL:
TRACE_INSN (cpu, "jal %s, %" PRIiTW ";", rd_name,
EXTRACT_JTYPE_IMM (iw));
store_rd (cpu, rd, riscv_cpu->pc + 4);
pc = riscv_cpu->pc + EXTRACT_JTYPE_IMM (iw);
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
break;
case MATCH_JALR:
TRACE_INSN (cpu, "jalr %s, %s, %" PRIiTW ";", rd_name, rs1_name, i_imm);
pc = riscv_cpu->regs[rs1] + i_imm;
store_rd (cpu, rd, riscv_cpu->pc + 4);
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
break;
case MATCH_LD:
TRACE_INSN (cpu, "ld %s, %" PRIiTW "(%s);",
rd_name, i_imm, rs1_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd,
sim_core_read_unaligned_8 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1] + i_imm));
break;
case MATCH_LW:
TRACE_INSN (cpu, "lw %s, %" PRIiTW "(%s);",
rd_name, i_imm, rs1_name);
store_rd (cpu, rd, EXTEND32 (
sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1] + i_imm)));
break;
case MATCH_LWU:
TRACE_INSN (cpu, "lwu %s, %" PRIiTW "(%s);",
rd_name, i_imm, rs1_name);
store_rd (cpu, rd,
sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1] + i_imm));
break;
case MATCH_LH:
TRACE_INSN (cpu, "lh %s, %" PRIiTW "(%s);",
rd_name, i_imm, rs1_name);
store_rd (cpu, rd, EXTEND16 (
sim_core_read_unaligned_2 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1] + i_imm)));
break;
case MATCH_LHU:
TRACE_INSN (cpu, "lbu %s, %" PRIiTW "(%s);",
rd_name, i_imm, rs1_name);
store_rd (cpu, rd,
sim_core_read_unaligned_2 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1] + i_imm));
break;
case MATCH_LB:
TRACE_INSN (cpu, "lb %s, %" PRIiTW "(%s);",
rd_name, i_imm, rs1_name);
store_rd (cpu, rd, EXTEND8 (
sim_core_read_unaligned_1 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1] + i_imm)));
break;
case MATCH_LBU:
TRACE_INSN (cpu, "lbu %s, %" PRIiTW "(%s);",
rd_name, i_imm, rs1_name);
store_rd (cpu, rd,
sim_core_read_unaligned_1 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1] + i_imm));
break;
case MATCH_SD:
TRACE_INSN (cpu, "sd %s, %" PRIiTW "(%s);",
rs2_name, s_imm, rs1_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
sim_core_write_unaligned_8 (cpu, riscv_cpu->pc, write_map,
riscv_cpu->regs[rs1] + s_imm,
riscv_cpu->regs[rs2]);
break;
case MATCH_SW:
TRACE_INSN (cpu, "sw %s, %" PRIiTW "(%s);",
rs2_name, s_imm, rs1_name);
sim_core_write_unaligned_4 (cpu, riscv_cpu->pc, write_map,
riscv_cpu->regs[rs1] + s_imm,
riscv_cpu->regs[rs2]);
break;
case MATCH_SH:
TRACE_INSN (cpu, "sh %s, %" PRIiTW "(%s);",
rs2_name, s_imm, rs1_name);
sim_core_write_unaligned_2 (cpu, riscv_cpu->pc, write_map,
riscv_cpu->regs[rs1] + s_imm,
riscv_cpu->regs[rs2]);
break;
case MATCH_SB:
TRACE_INSN (cpu, "sb %s, %" PRIiTW "(%s);",
rs2_name, s_imm, rs1_name);
sim_core_write_unaligned_1 (cpu, riscv_cpu->pc, write_map,
riscv_cpu->regs[rs1] + s_imm,
riscv_cpu->regs[rs2]);
break;
case MATCH_CSRRC:
TRACE_INSN (cpu, "csrrc");
switch (csr)
{
#define DECLARE_CSR(name, num, ...) \
case num: \
store_rd (cpu, rd, \
fetch_csr (cpu, #name, num, &riscv_cpu->csr.name)); \
store_csr (cpu, #name, num, &riscv_cpu->csr.name, \
riscv_cpu->csr.name & !riscv_cpu->regs[rs1]); \
break;
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
}
break;
case MATCH_CSRRS:
TRACE_INSN (cpu, "csrrs");
switch (csr)
{
#define DECLARE_CSR(name, num, ...) \
case num: \
store_rd (cpu, rd, \
fetch_csr (cpu, #name, num, &riscv_cpu->csr.name)); \
store_csr (cpu, #name, num, &riscv_cpu->csr.name, \
riscv_cpu->csr.name | riscv_cpu->regs[rs1]); \
break;
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
}
break;
case MATCH_CSRRW:
TRACE_INSN (cpu, "csrrw");
switch (csr)
{
#define DECLARE_CSR(name, num, ...) \
case num: \
store_rd (cpu, rd, \
fetch_csr (cpu, #name, num, &riscv_cpu->csr.name)); \
store_csr (cpu, #name, num, &riscv_cpu->csr.name, \
riscv_cpu->regs[rs1]); \
break;
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
}
break;
case MATCH_RDCYCLE:
TRACE_INSN (cpu, "rdcycle %s;", rd_name);
store_rd (cpu, rd,
fetch_csr (cpu, "cycle", CSR_CYCLE, &riscv_cpu->csr.cycle));
break;
case MATCH_RDCYCLEH:
TRACE_INSN (cpu, "rdcycleh %s;", rd_name);
RISCV_ASSERT_RV32 (cpu, "insn: %s", op->name);
store_rd (cpu, rd,
fetch_csr (cpu, "cycleh", CSR_CYCLEH, &riscv_cpu->csr.cycleh));
break;
case MATCH_RDINSTRET:
TRACE_INSN (cpu, "rdinstret %s;", rd_name);
store_rd (cpu, rd,
fetch_csr (cpu, "instret", CSR_INSTRET,
&riscv_cpu->csr.instret));
break;
case MATCH_RDINSTRETH:
TRACE_INSN (cpu, "rdinstreth %s;", rd_name);
RISCV_ASSERT_RV32 (cpu, "insn: %s", op->name);
store_rd (cpu, rd,
fetch_csr (cpu, "instreth", CSR_INSTRETH,
&riscv_cpu->csr.instreth));
break;
case MATCH_RDTIME:
TRACE_INSN (cpu, "rdtime %s;", rd_name);
store_rd (cpu, rd,
fetch_csr (cpu, "time", CSR_TIME, &riscv_cpu->csr.time));
break;
case MATCH_RDTIMEH:
TRACE_INSN (cpu, "rdtimeh %s;", rd_name);
RISCV_ASSERT_RV32 (cpu, "insn: %s", op->name);
store_rd (cpu, rd,
fetch_csr (cpu, "timeh", CSR_TIMEH, &riscv_cpu->csr.timeh));
break;
case MATCH_FENCE:
TRACE_INSN (cpu, "fence;");
break;
case MATCH_FENCE_I:
TRACE_INSN (cpu, "fence.i;");
break;
case MATCH_EBREAK:
TRACE_INSN (cpu, "ebreak;");
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_stopped, SIM_SIGTRAP);
break;
case MATCH_ECALL:
TRACE_INSN (cpu, "ecall;");
riscv_cpu->a0 = sim_syscall (cpu, riscv_cpu->a7, riscv_cpu->a0,
riscv_cpu->a1, riscv_cpu->a2, riscv_cpu->a3);
break;
default:
TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
}
return pc;
}
static uint64_t
mulhu (uint64_t a, uint64_t b)
{
#ifdef HAVE___INT128
return ((__int128)a * b) >> 64;
#else
uint64_t t;
uint32_t y1, y2, y3;
uint64_t a0 = (uint32_t)a, a1 = a >> 32;
uint64_t b0 = (uint32_t)b, b1 = b >> 32;
t = a1*b0 + ((a0*b0) >> 32);
y1 = t;
y2 = t >> 32;
t = a0*b1 + y1;
y1 = t;
t = a1*b1 + y2 + (t >> 32);
y2 = t;
y3 = t >> 32;
return ((uint64_t)y3 << 32) | y2;
#endif
}
static uint64_t
mulh (int64_t a, int64_t b)
{
int negate = (a < 0) != (b < 0);
uint64_t res = mulhu (a < 0 ? -a : a, b < 0 ? -b : b);
return negate ? ~res + (a * b == 0) : res;
}
static uint64_t
mulhsu (int64_t a, uint64_t b)
{
int negate = a < 0;
uint64_t res = mulhu (a < 0 ? -a : a, b);
return negate ? ~res + (a * b == 0) : res;
}
static sim_cia
execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
{
struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
SIM_DESC sd = CPU_STATE (cpu);
int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
int rs2 = (iw >> OP_SH_RS2) & OP_MASK_RS2;
const char *rd_name = riscv_gpr_names_abi[rd];
const char *rs1_name = riscv_gpr_names_abi[rs1];
const char *rs2_name = riscv_gpr_names_abi[rs2];
unsigned_word tmp, dividend_max;
sim_cia pc = riscv_cpu->pc + 4;
dividend_max = -((unsigned_word) 1 << (WITH_TARGET_WORD_BITSIZE - 1));
switch (op->match)
{
case MATCH_DIV:
TRACE_INSN (cpu, "div %s, %s, %s; // %s = %s / %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
if (riscv_cpu->regs[rs1] == dividend_max && riscv_cpu->regs[rs2] == -1)
tmp = dividend_max;
else if (riscv_cpu->regs[rs2])
tmp = (signed_word) riscv_cpu->regs[rs1] /
(signed_word) riscv_cpu->regs[rs2];
else
tmp = -1;
store_rd (cpu, rd, tmp);
break;
case MATCH_DIVW:
TRACE_INSN (cpu, "divw %s, %s, %s; // %s = %s / %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
if (EXTEND32 (riscv_cpu->regs[rs2]) == -1)
tmp = 1 << 31;
else if (EXTEND32 (riscv_cpu->regs[rs2]))
tmp = EXTEND32 (riscv_cpu->regs[rs1]) / EXTEND32 (riscv_cpu->regs[rs2]);
else
tmp = -1;
store_rd (cpu, rd, EXTEND32 (tmp));
break;
case MATCH_DIVU:
TRACE_INSN (cpu, "divu %s, %s, %s; // %s = %s / %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
if (riscv_cpu->regs[rs2])
store_rd (cpu, rd, (unsigned_word) riscv_cpu->regs[rs1]
/ (unsigned_word) riscv_cpu->regs[rs2]);
else
store_rd (cpu, rd, -1);
break;
case MATCH_DIVUW:
TRACE_INSN (cpu, "divuw %s, %s, %s; // %s = %s / %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
if ((uint32_t) riscv_cpu->regs[rs2])
tmp = (uint32_t) riscv_cpu->regs[rs1] / (uint32_t) riscv_cpu->regs[rs2];
else
tmp = -1;
store_rd (cpu, rd, EXTEND32 (tmp));
break;
case MATCH_MUL:
TRACE_INSN (cpu, "mul %s, %s, %s; // %s = %s * %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
store_rd (cpu, rd, riscv_cpu->regs[rs1] * riscv_cpu->regs[rs2]);
break;
case MATCH_MULW:
TRACE_INSN (cpu, "mulw %s, %s, %s; // %s = %s * %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd, EXTEND32 ((int32_t) riscv_cpu->regs[rs1]
* (int32_t) riscv_cpu->regs[rs2]));
break;
case MATCH_MULH:
TRACE_INSN (cpu, "mulh %s, %s, %s; // %s = %s * %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
if (RISCV_XLEN (cpu) == 32)
store_rd (cpu, rd,
((int64_t)(signed_word) riscv_cpu->regs[rs1]
* (int64_t)(signed_word) riscv_cpu->regs[rs2]) >> 32);
else
store_rd (cpu, rd, mulh (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2]));
break;
case MATCH_MULHU:
TRACE_INSN (cpu, "mulhu %s, %s, %s; // %s = %s * %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
if (RISCV_XLEN (cpu) == 32)
store_rd (cpu, rd, ((uint64_t)riscv_cpu->regs[rs1]
* (uint64_t)riscv_cpu->regs[rs2]) >> 32);
else
store_rd (cpu, rd, mulhu (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2]));
break;
case MATCH_MULHSU:
TRACE_INSN (cpu, "mulhsu %s, %s, %s; // %s = %s * %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
if (RISCV_XLEN (cpu) == 32)
store_rd (cpu, rd, ((int64_t)(signed_word) riscv_cpu->regs[rs1]
* (uint64_t)riscv_cpu->regs[rs2]) >> 32);
else
store_rd (cpu, rd, mulhsu (riscv_cpu->regs[rs1], riscv_cpu->regs[rs2]));
break;
case MATCH_REM:
TRACE_INSN (cpu, "rem %s, %s, %s; // %s = %s %% %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
if (riscv_cpu->regs[rs1] == dividend_max && riscv_cpu->regs[rs2] == -1)
tmp = 0;
else if (riscv_cpu->regs[rs2])
tmp = (signed_word) riscv_cpu->regs[rs1]
% (signed_word) riscv_cpu->regs[rs2];
else
tmp = riscv_cpu->regs[rs1];
store_rd (cpu, rd, tmp);
break;
case MATCH_REMW:
TRACE_INSN (cpu, "remw %s, %s, %s; // %s = %s %% %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
if (EXTEND32 (riscv_cpu->regs[rs2]) == -1)
tmp = 0;
else if (EXTEND32 (riscv_cpu->regs[rs2]))
tmp = EXTEND32 (riscv_cpu->regs[rs1]) % EXTEND32 (riscv_cpu->regs[rs2]);
else
tmp = riscv_cpu->regs[rs1];
store_rd (cpu, rd, EXTEND32 (tmp));
break;
case MATCH_REMU:
TRACE_INSN (cpu, "remu %s, %s, %s; // %s = %s %% %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
if (riscv_cpu->regs[rs2])
store_rd (cpu, rd, riscv_cpu->regs[rs1] % riscv_cpu->regs[rs2]);
else
store_rd (cpu, rd, riscv_cpu->regs[rs1]);
break;
case MATCH_REMUW:
TRACE_INSN (cpu, "remuw %s, %s, %s; // %s = %s %% %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
if ((uint32_t) riscv_cpu->regs[rs2])
tmp = (uint32_t) riscv_cpu->regs[rs1] % (uint32_t) riscv_cpu->regs[rs2];
else
tmp = riscv_cpu->regs[rs1];
store_rd (cpu, rd, EXTEND32 (tmp));
break;
default:
TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
}
return pc;
}
static sim_cia
execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
{
struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
SIM_DESC sd = CPU_STATE (cpu);
struct riscv_sim_state *state = RISCV_SIM_STATE (sd);
int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
int rs2 = (iw >> OP_SH_RS2) & OP_MASK_RS2;
const char *rd_name = riscv_gpr_names_abi[rd];
const char *rs1_name = riscv_gpr_names_abi[rs1];
const char *rs2_name = riscv_gpr_names_abi[rs2];
struct atomic_mem_reserved_list *amo_prev, *amo_curr;
unsigned_word tmp;
sim_cia pc = riscv_cpu->pc + 4;
/* Handle these two load/store operations specifically. */
switch (op->match)
{
case MATCH_LR_W:
TRACE_INSN (cpu, "%s %s, (%s);", op->name, rd_name, rs1_name);
store_rd (cpu, rd,
sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1]));
/* Walk the reservation list to find an existing match. */
amo_curr = state->amo_reserved_list;
while (amo_curr)
{
if (amo_curr->addr == riscv_cpu->regs[rs1])
goto done;
amo_curr = amo_curr->next;
}
/* No reservation exists, so add one. */
amo_curr = xmalloc (sizeof (*amo_curr));
amo_curr->addr = riscv_cpu->regs[rs1];
amo_curr->next = state->amo_reserved_list;
state->amo_reserved_list = amo_curr;
goto done;
case MATCH_SC_W:
TRACE_INSN (cpu, "%s %s, %s, (%s);", op->name, rd_name, rs2_name,
rs1_name);
/* Walk the reservation list to find a match. */
amo_curr = amo_prev = state->amo_reserved_list;
while (amo_curr)
{
if (amo_curr->addr == riscv_cpu->regs[rs1])
{
/* We found a reservation, so operate it. */
sim_core_write_unaligned_4 (cpu, riscv_cpu->pc, write_map,
riscv_cpu->regs[rs1],
riscv_cpu->regs[rs2]);
store_rd (cpu, rd, 0);
if (amo_curr == state->amo_reserved_list)
state->amo_reserved_list = amo_curr->next;
else
amo_prev->next = amo_curr->next;
free (amo_curr);
goto done;
}
amo_prev = amo_curr;
amo_curr = amo_curr->next;
}
/* If we're still here, then no reservation exists, so mark as failed. */
store_rd (cpu, rd, 1);
goto done;
}
/* Handle the rest of the atomic insns with common code paths. */
TRACE_INSN (cpu, "%s %s, %s, (%s);",
op->name, rd_name, rs2_name, rs1_name);
if (op->xlen_requirement == 64)
tmp = sim_core_read_unaligned_8 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1]);
else
tmp = EXTEND32 (sim_core_read_unaligned_4 (cpu, riscv_cpu->pc, read_map,
riscv_cpu->regs[rs1]));
store_rd (cpu, rd, tmp);
switch (op->match)
{
case MATCH_AMOADD_D:
case MATCH_AMOADD_W:
tmp = riscv_cpu->regs[rd] + riscv_cpu->regs[rs2];
break;
case MATCH_AMOAND_D:
case MATCH_AMOAND_W:
tmp = riscv_cpu->regs[rd] & riscv_cpu->regs[rs2];
break;
case MATCH_AMOMAX_D:
case MATCH_AMOMAX_W:
tmp = max ((signed_word) riscv_cpu->regs[rd],
(signed_word) riscv_cpu->regs[rs2]);
break;
case MATCH_AMOMAXU_D:
case MATCH_AMOMAXU_W:
tmp = max ((unsigned_word) riscv_cpu->regs[rd],
(unsigned_word) riscv_cpu->regs[rs2]);
break;
case MATCH_AMOMIN_D:
case MATCH_AMOMIN_W:
tmp = min ((signed_word) riscv_cpu->regs[rd],
(signed_word) riscv_cpu->regs[rs2]);
break;
case MATCH_AMOMINU_D:
case MATCH_AMOMINU_W:
tmp = min ((unsigned_word) riscv_cpu->regs[rd],
(unsigned_word) riscv_cpu->regs[rs2]);
break;
case MATCH_AMOOR_D:
case MATCH_AMOOR_W:
tmp = riscv_cpu->regs[rd] | riscv_cpu->regs[rs2];
break;
case MATCH_AMOSWAP_D:
case MATCH_AMOSWAP_W:
tmp = riscv_cpu->regs[rs2];
break;
case MATCH_AMOXOR_D:
case MATCH_AMOXOR_W:
tmp = riscv_cpu->regs[rd] ^ riscv_cpu->regs[rs2];
break;
default:
TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
}
if (op->xlen_requirement == 64)
sim_core_write_unaligned_8 (cpu, riscv_cpu->pc, write_map,
riscv_cpu->regs[rs1], tmp);
else
sim_core_write_unaligned_4 (cpu, riscv_cpu->pc, write_map,
riscv_cpu->regs[rs1], tmp);
done:
return pc;
}
static sim_cia
execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
{
SIM_DESC sd = CPU_STATE (cpu);
struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
int rs1_c = ((iw >> OP_SH_CRS1S) & OP_MASK_CRS1S) + 8;
int rs2 = (iw >> OP_SH_CRS2) & OP_MASK_CRS2;
int rs2_c = ((iw >> OP_SH_CRS2S) & OP_MASK_CRS2S) + 8;
const char *rd_name = riscv_gpr_names_abi[rd];
const char *rs1_c_name = riscv_gpr_names_abi[rs1_c];
const char *rs2_name = riscv_gpr_names_abi[rs2];
const char *rs2_c_name = riscv_gpr_names_abi[rs2_c];
signed_word imm;
unsigned_word tmp;
sim_cia pc = riscv_cpu->pc + 2;
switch (op->match)
{
case MATCH_C_JR | MATCH_C_MV:
switch (op->mask)
{
case MASK_C_MV:
TRACE_INSN (cpu, "c.mv %s, %s; // %s = %s",
rd_name, rs2_name, rd_name, rs2_name);
store_rd (cpu, rd, riscv_cpu->regs[rs2]);
break;