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interp.c
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/* Simulator for the Renesas (formerly Hitachi) / SuperH Inc. SH architecture.
Written by Steve Chamberlain of Cygnus Support.
This file is part of SH sim
THIS SOFTWARE IS NOT COPYRIGHTED
Cygnus offers the following for use in the public domain. Cygnus
makes no warranty with regard to the software or it's performance
and the user accepts the software "AS IS" with all faults.
CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
/* This must come before any other includes. */
#include "defs.h"
#include <ctype.h>
#include <stdio.h>
#include <errno.h>
#include <signal.h>
#include <unistd.h>
#ifdef HAVE_MMAP
#include <sys/mman.h>
# ifndef MAP_FAILED
# define MAP_FAILED -1
# endif
# if !defined (MAP_ANONYMOUS) && defined (MAP_ANON)
# define MAP_ANONYMOUS MAP_ANON
# endif
#endif
#include <string.h>
#include <stdlib.h>
#include <sys/stat.h>
#include <time.h>
#include <sys/time.h>
#ifdef HAVE_UTIME_H
#include <utime.h>
#endif
#ifndef _WIN32
#include <sys/wait.h>
#endif
#include "bfd.h"
#include "sim/callback.h"
#include "sim/sim.h"
#include "sim/sim-sh.h"
#include "sim-main.h"
#include "sim-base.h"
#include "sim-options.h"
#include "target-newlib-syscall.h"
#include "sh-sim.h"
#include <math.h>
#ifdef _WIN32
#include <float.h> /* Needed for _isnan() */
#ifndef isnan
#define isnan _isnan
#endif
#endif
#ifndef SIGBUS
#define SIGBUS SIGSEGV
#endif
#ifndef SIGQUIT
#define SIGQUIT SIGTERM
#endif
#ifndef SIGTRAP
#define SIGTRAP 5
#endif
/* TODO: Stop using these names. */
#undef SEXT
#undef SEXT32
extern unsigned short sh_jump_table[], sh_dsp_table[0x1000], ppi_table[];
#define O_RECOMPILE 85
#define DEFINE_TABLE
#define DISASSEMBLER_TABLE
/* Define the rate at which the simulator should poll the host
for a quit. */
#define POLL_QUIT_INTERVAL 0x60000
/* TODO: Move into sim_cpu. */
saved_state_type saved_state;
struct loop_bounds { unsigned char *start, *end; };
/* These variables are at file scope so that functions other than
sim_resume can use the fetch/store macros */
#define target_little_endian (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
static int global_endianw, endianb;
static int target_dsp;
#define host_little_endian (HOST_BYTE_ORDER == BFD_ENDIAN_LITTLE)
static int maskw = 0;
static int maskl = 0;
/* Short hand definitions of the registers */
#define SBIT(x) ((x)&sbit)
#define R0 saved_state.asregs.regs[0]
#define Rn saved_state.asregs.regs[n]
#define Rm saved_state.asregs.regs[m]
#define UR0 (unsigned int) (saved_state.asregs.regs[0])
#define UR (unsigned int) R
#define UR (unsigned int) R
#define SR0 saved_state.asregs.regs[0]
#define CREG(n) (saved_state.asregs.cregs[(n)])
#define GBR saved_state.asregs.gbr
#define VBR saved_state.asregs.vbr
#define DBR saved_state.asregs.dbr
#define TBR saved_state.asregs.tbr
#define IBCR saved_state.asregs.ibcr
#define IBNR saved_state.asregs.ibnr
#define BANKN (saved_state.asregs.ibnr & 0x1ff)
#define ME ((saved_state.asregs.ibnr >> 14) & 0x3)
#define SSR saved_state.asregs.ssr
#define SPC saved_state.asregs.spc
#define SGR saved_state.asregs.sgr
#define SREG(n) (saved_state.asregs.sregs[(n)])
#define MACH saved_state.asregs.mach
#define MACL saved_state.asregs.macl
#define PR saved_state.asregs.pr
#define FPUL saved_state.asregs.fpul
#define PC insn_ptr
/* Alternate bank of registers r0-r7 */
/* Note: code controlling SR handles flips between BANK0 and BANK1 */
#define Rn_BANK(n) (saved_state.asregs.bank[(n)])
#define SET_Rn_BANK(n, EXP) do { saved_state.asregs.bank[(n)] = (EXP); } while (0)
/* Manipulate SR */
#define SR_MASK_BO (1 << 14)
#define SR_MASK_CS (1 << 13)
#define SR_MASK_DMY (1 << 11)
#define SR_MASK_DMX (1 << 10)
#define SR_MASK_M (1 << 9)
#define SR_MASK_Q (1 << 8)
#define SR_MASK_I (0xf << 4)
#define SR_MASK_S (1 << 1)
#define SR_MASK_T (1 << 0)
#define SR_MASK_BL (1 << 28)
#define SR_MASK_RB (1 << 29)
#define SR_MASK_MD (1 << 30)
#define SR_MASK_RC 0x0fff0000
#define SR_RC_INCREMENT -0x00010000
#define BO ((saved_state.asregs.sr & SR_MASK_BO) != 0)
#define CS ((saved_state.asregs.sr & SR_MASK_CS) != 0)
#define M ((saved_state.asregs.sr & SR_MASK_M) != 0)
#define Q ((saved_state.asregs.sr & SR_MASK_Q) != 0)
#define S ((saved_state.asregs.sr & SR_MASK_S) != 0)
#define T ((saved_state.asregs.sr & SR_MASK_T) != 0)
#define LDST ((saved_state.asregs.ldst) != 0)
#define SR_BL ((saved_state.asregs.sr & SR_MASK_BL) != 0)
#define SR_RB ((saved_state.asregs.sr & SR_MASK_RB) != 0)
#define SR_MD ((saved_state.asregs.sr & SR_MASK_MD) != 0)
#define SR_DMY ((saved_state.asregs.sr & SR_MASK_DMY) != 0)
#define SR_DMX ((saved_state.asregs.sr & SR_MASK_DMX) != 0)
#define SR_RC ((saved_state.asregs.sr & SR_MASK_RC))
/* Note: don't use this for privileged bits */
#define SET_SR_BIT(EXP, BIT) \
do { \
if ((EXP) & 1) \
saved_state.asregs.sr |= (BIT); \
else \
saved_state.asregs.sr &= ~(BIT); \
} while (0)
#define SET_SR_BO(EXP) SET_SR_BIT ((EXP), SR_MASK_BO)
#define SET_SR_CS(EXP) SET_SR_BIT ((EXP), SR_MASK_CS)
#define SET_BANKN(EXP) \
do { \
IBNR = (IBNR & 0xfe00) | ((EXP) & 0x1f); \
} while (0)
#define SET_ME(EXP) \
do { \
IBNR = (IBNR & 0x3fff) | (((EXP) & 0x3) << 14); \
} while (0)
#define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
#define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
#define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
#define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
#define SET_LDST(EXP) (saved_state.asregs.ldst = ((EXP) != 0))
/* stc currently relies on being able to read SR without modifications. */
#define GET_SR() (saved_state.asregs.sr - 0)
#define SET_SR(x) set_sr (x)
#define SET_RC(x) \
(saved_state.asregs.sr \
= (saved_state.asregs.sr & 0xf000ffff) | ((x) & 0xfff) << 16)
/* Manipulate FPSCR */
#define FPSCR_MASK_FR (1 << 21)
#define FPSCR_MASK_SZ (1 << 20)
#define FPSCR_MASK_PR (1 << 19)
#define FPSCR_FR ((GET_FPSCR () & FPSCR_MASK_FR) != 0)
#define FPSCR_SZ ((GET_FPSCR () & FPSCR_MASK_SZ) != 0)
#define FPSCR_PR ((GET_FPSCR () & FPSCR_MASK_PR) != 0)
static void
set_fpscr1 (int x)
{
int old = saved_state.asregs.fpscr;
saved_state.asregs.fpscr = (x);
/* swap the floating point register banks */
if ((saved_state.asregs.fpscr ^ old) & FPSCR_MASK_FR
/* Ignore bit change if simulating sh-dsp. */
&& ! target_dsp)
{
union fregs_u tmpf = saved_state.asregs.fregs[0];
saved_state.asregs.fregs[0] = saved_state.asregs.fregs[1];
saved_state.asregs.fregs[1] = tmpf;
}
}
/* sts relies on being able to read fpscr directly. */
#define GET_FPSCR() (saved_state.asregs.fpscr)
#define SET_FPSCR(x) \
do { \
set_fpscr1 (x); \
} while (0)
#define DSR (saved_state.asregs.fpscr)
#define RAISE_EXCEPTION(x) \
(saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0)
#define RAISE_EXCEPTION_IF_IN_DELAY_SLOT() \
if (in_delay_slot) RAISE_EXCEPTION (SIGILL)
/* This function exists mainly for the purpose of setting a breakpoint to
catch simulated bus errors when running the simulator under GDB. */
static void
raise_exception (int x)
{
RAISE_EXCEPTION (x);
}
static void
raise_buserror (void)
{
raise_exception (SIGBUS);
}
#define PROCESS_SPECIAL_ADDRESS(addr, endian, ptr, bits_written, \
forbidden_addr_bits, data, retval) \
do { \
if (addr & forbidden_addr_bits) \
{ \
raise_buserror (); \
return retval; \
} \
else if ((addr & saved_state.asregs.xyram_select) \
== saved_state.asregs.xram_start) \
ptr = (void *) &saved_state.asregs.xmem_offset[addr ^ endian]; \
else if ((addr & saved_state.asregs.xyram_select) \
== saved_state.asregs.yram_start) \
ptr = (void *) &saved_state.asregs.ymem_offset[addr ^ endian]; \
else if ((unsigned) addr >> 24 == 0xf0 \
&& bits_written == 32 && (data & 1) == 0) \
/* This invalidates (if not associative) or might invalidate \
(if associative) an instruction cache line. This is used for \
trampolines. Since we don't simulate the cache, this is a no-op \
as far as the simulator is concerned. */ \
return retval; \
else \
{ \
if (bits_written == 8 && addr > 0x5000000) \
IOMEM (addr, 1, data); \
/* We can't do anything useful with the other stuff, so fail. */ \
raise_buserror (); \
return retval; \
} \
} while (0)
/* FIXME: sim_resume should be renamed to sim_engine_run. sim_resume
being implemented by ../common/sim_resume.c and the below should
make a call to sim_engine_halt */
#define BUSERROR(addr, mask) ((addr) & (mask))
#define WRITE_BUSERROR(addr, mask, data, addr_func) \
do \
{ \
if (addr & mask) \
{ \
addr_func (addr, data); \
return; \
} \
} \
while (0)
#define READ_BUSERROR(addr, mask, addr_func) \
do \
{ \
if (addr & mask) \
return addr_func (addr); \
} \
while (0)
/* Define this to enable register lifetime checking.
The compiler generates "add #0,rn" insns to mark registers as invalid,
the simulator uses this info to call fail if it finds a ref to an invalid
register before a def
#define PARANOID
*/
#ifdef PARANOID
int valid[16];
#define CREF(x) if (!valid[x]) fail ();
#define CDEF(x) valid[x] = 1;
#define UNDEF(x) valid[x] = 0;
#else
#define CREF(x)
#define CDEF(x)
#define UNDEF(x)
#endif
static void parse_and_set_memory_size (SIM_DESC sd, const char *str);
static int IOMEM (int addr, int write, int value);
static struct loop_bounds get_loop_bounds (int, int, unsigned char *,
unsigned char *, int, int);
static void process_wlat_addr (int, int);
static void process_wwat_addr (int, int);
static void process_wbat_addr (int, int);
static int process_rlat_addr (int);
static int process_rwat_addr (int);
static int process_rbat_addr (int);
/* Floating point registers */
#define DR(n) (get_dr (n))
static double
get_dr (int n)
{
n = (n & ~1);
if (host_little_endian)
{
union
{
int i[2];
double d;
} dr;
dr.i[1] = saved_state.asregs.fregs[0].i[n + 0];
dr.i[0] = saved_state.asregs.fregs[0].i[n + 1];
return dr.d;
}
else
return (saved_state.asregs.fregs[0].d[n >> 1]);
}
#define SET_DR(n, EXP) set_dr ((n), (EXP))
static void
set_dr (int n, double exp)
{
n = (n & ~1);
if (host_little_endian)
{
union
{
int i[2];
double d;
} dr;
dr.d = exp;
saved_state.asregs.fregs[0].i[n + 0] = dr.i[1];
saved_state.asregs.fregs[0].i[n + 1] = dr.i[0];
}
else
saved_state.asregs.fregs[0].d[n >> 1] = exp;
}
#define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP))
#define FI(n) (saved_state.asregs.fregs[0].i[(n)])
#define FR(n) (saved_state.asregs.fregs[0].f[(n)])
#define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP))
#define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e))
#define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f])
#define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP))
#define RS saved_state.asregs.rs
#define RE saved_state.asregs.re
#define MOD (saved_state.asregs.mod)
#define SET_MOD(i) \
(MOD = (i), \
MOD_ME = (unsigned) MOD >> 16 | (SR_DMY ? ~0xffff : (SR_DMX ? 0 : 0x10000)), \
MOD_DELTA = (MOD & 0xffff) - ((unsigned) MOD >> 16))
#define DSP_R(n) saved_state.asregs.sregs[(n)]
#define DSP_GRD(n) DSP_R ((n) + 8)
#define GET_DSP_GRD(n) ((n | 2) == 7 ? SEXT (DSP_GRD (n)) : SIGN32 (DSP_R (n)))
#define A1 DSP_R (5)
#define A0 DSP_R (7)
#define X0 DSP_R (8)
#define X1 DSP_R (9)
#define Y0 DSP_R (10)
#define Y1 DSP_R (11)
#define M0 DSP_R (12)
#define A1G DSP_R (13)
#define M1 DSP_R (14)
#define A0G DSP_R (15)
/* DSP_R (16) / DSP_GRD (16) are used as a fake destination for pcmp. */
#define MOD_ME DSP_GRD (17)
#define MOD_DELTA DSP_GRD (18)
#define FP_OP(n, OP, m) \
{ \
if (FPSCR_PR) \
{ \
if (((n) & 1) || ((m) & 1)) \
RAISE_EXCEPTION (SIGILL); \
else \
SET_DR (n, (DR (n) OP DR (m))); \
} \
else \
SET_FR (n, (FR (n) OP FR (m))); \
} while (0)
#define FP_UNARY(n, OP) \
{ \
if (FPSCR_PR) \
{ \
if ((n) & 1) \
RAISE_EXCEPTION (SIGILL); \
else \
SET_DR (n, (OP (DR (n)))); \
} \
else \
SET_FR (n, (OP (FR (n)))); \
} while (0)
#define FP_CMP(n, OP, m) \
{ \
if (FPSCR_PR) \
{ \
if (((n) & 1) || ((m) & 1)) \
RAISE_EXCEPTION (SIGILL); \
else \
SET_SR_T (DR (n) OP DR (m)); \
} \
else \
SET_SR_T (FR (n) OP FR (m)); \
} while (0)
static void
set_sr (int new_sr)
{
/* do we need to swap banks */
int old_gpr = SR_MD && SR_RB;
int new_gpr = (new_sr & SR_MASK_MD) && (new_sr & SR_MASK_RB);
if (old_gpr != new_gpr)
{
int i, tmp;
for (i = 0; i < 8; i++)
{
tmp = saved_state.asregs.bank[i];
saved_state.asregs.bank[i] = saved_state.asregs.regs[i];
saved_state.asregs.regs[i] = tmp;
}
}
saved_state.asregs.sr = new_sr;
SET_MOD (MOD);
}
static INLINE void
wlat_fast (unsigned char *memory, int x, int value, int maskl)
{
int v = value;
unsigned int *p = (unsigned int *) (memory + x);
WRITE_BUSERROR (x, maskl, v, process_wlat_addr);
*p = v;
}
static INLINE void
wwat_fast (unsigned char *memory, int x, int value, int maskw, int endianw)
{
int v = value;
unsigned short *p = (unsigned short *) (memory + (x ^ endianw));
WRITE_BUSERROR (x, maskw, v, process_wwat_addr);
*p = v;
}
static INLINE void
wbat_fast (unsigned char *memory, int x, int value, int maskb)
{
unsigned char *p = memory + (x ^ endianb);
WRITE_BUSERROR (x, maskb, value, process_wbat_addr);
p[0] = value;
}
/* Read functions */
static INLINE int
rlat_fast (unsigned char *memory, int x, int maskl)
{
unsigned int *p = (unsigned int *) (memory + x);
READ_BUSERROR (x, maskl, process_rlat_addr);
return *p;
}
static INLINE int
rwat_fast (unsigned char *memory, int x, int maskw, int endianw)
{
unsigned short *p = (unsigned short *) (memory + (x ^ endianw));
READ_BUSERROR (x, maskw, process_rwat_addr);
return *p;
}
static INLINE int
riat_fast (unsigned char *insn_ptr, int endianw)
{
unsigned short *p = (unsigned short *) ((uintptr_t) insn_ptr ^ endianw);
return *p;
}
static INLINE int
rbat_fast (unsigned char *memory, int x, int maskb)
{
unsigned char *p = memory + (x ^ endianb);
READ_BUSERROR (x, maskb, process_rbat_addr);
return *p;
}
#define RWAT(x) (rwat_fast (memory, x, maskw, endianw))
#define RLAT(x) (rlat_fast (memory, x, maskl))
#define RBAT(x) (rbat_fast (memory, x, maskb))
#define RIAT(p) (riat_fast ((p), endianw))
#define WWAT(x,v) (wwat_fast (memory, x, v, maskw, endianw))
#define WLAT(x,v) (wlat_fast (memory, x, v, maskl))
#define WBAT(x,v) (wbat_fast (memory, x, v, maskb))
#define RUWAT(x) (RWAT (x) & 0xffff)
#define RSWAT(x) ((short) (RWAT (x)))
#define RSLAT(x) ((long) (RLAT (x)))
#define RSBAT(x) (SEXT (RBAT (x)))
#define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl)))
static int
do_rdat (unsigned char *memory, int x, int n, int maskl)
{
int f0;
int f1;
int i = (n & 1);
int j = (n & ~1);
f0 = rlat_fast (memory, x + 0, maskl);
f1 = rlat_fast (memory, x + 4, maskl);
saved_state.asregs.fregs[i].i[(j + 0)] = f0;
saved_state.asregs.fregs[i].i[(j + 1)] = f1;
return 0;
}
#define WDAT(x, n) (do_wdat (memory, (x), (n), (maskl)))
static int
do_wdat (unsigned char *memory, int x, int n, int maskl)
{
int f0;
int f1;
int i = (n & 1);
int j = (n & ~1);
f0 = saved_state.asregs.fregs[i].i[(j + 0)];
f1 = saved_state.asregs.fregs[i].i[(j + 1)];
wlat_fast (memory, (x + 0), f0, maskl);
wlat_fast (memory, (x + 4), f1, maskl);
return 0;
}
static void
process_wlat_addr (int addr, int value)
{
unsigned int *ptr;
PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 32, 3, value, );
*ptr = value;
}
static void
process_wwat_addr (int addr, int value)
{
unsigned short *ptr;
PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 16, 1, value, );
*ptr = value;
}
static void
process_wbat_addr (int addr, int value)
{
unsigned char *ptr;
PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 8, 0, value, );
*ptr = value;
}
static int
process_rlat_addr (int addr)
{
unsigned char *ptr;
PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -32, 3, -1, 0);
return *ptr;
}
static int
process_rwat_addr (int addr)
{
unsigned char *ptr;
PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -16, 1, -1, 0);
return *ptr;
}
static int
process_rbat_addr (int addr)
{
unsigned char *ptr;
PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -8, 0, -1, 0);
return *ptr;
}
#define SEXT(x) (((x & 0xff) ^ (~0x7f))+0x80)
#define SEXT12(x) (((x & 0xfff) ^ 0x800) - 0x800)
#define SEXTW(y) ((int) ((short) y))
#if 0
#define SEXT32(x) ((int) ((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1)
#else
#define SEXT32(x) ((int) (x))
#endif
#define SIGN32(x) (SEXT32 (x) >> 31)
/* convert pointer from target to host value. */
#define PT2H(x) ((x) + memory)
/* convert pointer from host to target value. */
#define PH2T(x) ((x) - memory)
#define SKIP_INSN(p) ((p) += ((RIAT (p) & 0xfc00) == 0xf800 ? 4 : 2))
#define SET_NIP(x) nip = (x); CHECK_INSN_PTR (nip);
static int in_delay_slot = 0;
#define Delay_Slot(TEMPPC) iword = RIAT (TEMPPC); in_delay_slot = 1; goto top;
#define CHECK_INSN_PTR(p) \
do { \
if (saved_state.asregs.exception || PH2T (p) & maskw) \
saved_state.asregs.insn_end = 0; \
else if (p < loop.end) \
saved_state.asregs.insn_end = loop.end; \
else \
saved_state.asregs.insn_end = mem_end; \
} while (0)
#ifdef ACE_FAST
#define MA(n)
#define L(x)
#define TL(x)
#define TB(x)
#else
#define MA(n) \
do { memstalls += ((((uintptr_t) PC & 3) != 0) ? (n) : ((n) - 1)); } while (0)
#define L(x) thislock = x;
#define TL(x) if ((x) == prevlock) stalls++;
#define TB(x,y) if ((x) == prevlock || (y) == prevlock) stalls++;
#endif
#if defined(__GO32__)
int sim_memory_size = 19;
#else
int sim_memory_size = 30;
#endif
static int sim_profile_size = 17;
static int nsamples;
#undef TB
#define TB(x,y)
#define SMR1 (0x05FFFEC8) /* Channel 1 serial mode register */
#define BRR1 (0x05FFFEC9) /* Channel 1 bit rate register */
#define SCR1 (0x05FFFECA) /* Channel 1 serial control register */
#define TDR1 (0x05FFFECB) /* Channel 1 transmit data register */
#define SSR1 (0x05FFFECC) /* Channel 1 serial status register */
#define RDR1 (0x05FFFECD) /* Channel 1 receive data register */
#define SCI_RDRF 0x40 /* Receive data register full */
#define SCI_TDRE 0x80 /* Transmit data register empty */
static int
IOMEM (int addr, int write, int value)
{
if (write)
{
switch (addr)
{
case TDR1:
if (value != '\r')
{
putchar (value);
fflush (stdout);
}
break;
}
}
else
{
switch (addr)
{
case RDR1:
return getchar ();
}
}
return 0;
}
static int
get_now (void)
{
return time (NULL);
}
static int
now_persec (void)
{
return 1;
}
static FILE *profile_file;
static INLINE unsigned
swap (unsigned n)
{
if (endianb)
n = (n << 24 | (n & 0xff00) << 8
| (n & 0xff0000) >> 8 | (n & 0xff000000) >> 24);
return n;
}
static INLINE unsigned short
swap16 (unsigned short n)
{
if (endianb)
n = n << 8 | (n & 0xff00) >> 8;
return n;
}
static void
swapout (int n)
{
if (profile_file)
{
union { char b[4]; int n; } u;
u.n = swap (n);
fwrite (u.b, 4, 1, profile_file);
}
}
static void
swapout16 (int n)
{
union { char b[4]; int n; } u;
u.n = swap16 (n);
fwrite (u.b, 2, 1, profile_file);
}
/* Turn a pointer in a register into a pointer into real memory. */
static char *
ptr (int x)
{
return (char *) (x + saved_state.asregs.memory);
}
/* STR points to a zero-terminated string in target byte order. Return
the number of bytes that need to be converted to host byte order in order
to use this string as a zero-terminated string on the host.
(Not counting the rounding up needed to operate on entire words.) */
static int
strswaplen (int str)
{
unsigned char *memory = saved_state.asregs.memory;
int end;
int endian = endianb;
if (! endian)
return 0;
end = str;
for (end = str; memory[end ^ endian]; end++) ;
return end - str + 1;
}
static void
strnswap (int str, int len)
{
int *start, *end;
if (! endianb || ! len)
return;
start = (int *) ptr (str & ~3);
end = (int *) ptr (str + len);
do
{
int old = *start;
*start = (old << 24 | (old & 0xff00) << 8
| (old & 0xff0000) >> 8 | (old & 0xff000000) >> 24);
start++;
}
while (start < end);
}
/* Simulate a monitor trap, put the result into r0 and errno into r1
return offset by which to adjust pc. */
static int
trap (SIM_DESC sd, int i, int *regs, unsigned char *insn_ptr,
unsigned char *memory, int maskl, int maskw, int endianw)
{
host_callback *callback = STATE_CALLBACK (sd);
char **prog_argv = STATE_PROG_ARGV (sd);
switch (i)
{
case 1:
printf ("%c", regs[0]);
break;
case 2:
raise_exception (SIGQUIT);
break;
case 3: /* FIXME: for backwards compat, should be removed */
case 33:
{
unsigned int countp = * (unsigned int *) (insn_ptr + 4);
WLAT (countp, RLAT (countp) + 1);
return 6;
}
case 34:
{
int perrno = errno;
errno = 0;
switch (regs[4])
{
#if !defined(__GO32__) && !defined(_WIN32)
case TARGET_NEWLIB_SH_SYS_fork:
regs[0] = fork ();
break;
/* This would work only if endianness matched between host and target.
Besides, it's quite dangerous. */
#if 0
case TARGET_NEWLIB_SH_SYS_execve:
regs[0] = execve (ptr (regs[5]), (char **) ptr (regs[6]),
(char **) ptr (regs[7]));
break;
case TARGET_NEWLIB_SH_SYS_execv:
regs[0] = execve (ptr (regs[5]), (char **) ptr (regs[6]), 0);
break;
#endif
case TARGET_NEWLIB_SH_SYS_pipe:
{
regs[0] = (BUSERROR (regs[5], maskl)
? -EINVAL
: pipe ((int *) ptr (regs[5])));
}
break;
case TARGET_NEWLIB_SH_SYS_wait:
regs[0] = wait ((int *) ptr (regs[5]));
break;
#endif /* !defined(__GO32__) && !defined(_WIN32) */
case TARGET_NEWLIB_SH_SYS_read:
strnswap (regs[6], regs[7]);
regs[0]
= callback->read (callback, regs[5], ptr (regs[6]), regs[7]);
strnswap (regs[6], regs[7]);
break;
case TARGET_NEWLIB_SH_SYS_write:
strnswap (regs[6], regs[7]);
if (regs[5] == 1)
regs[0] = (int) callback->write_stdout (callback,
ptr (regs[6]), regs[7]);
else
regs[0] = (int) callback->write (callback, regs[5],
ptr (regs[6]), regs[7]);
strnswap (regs[6], regs[7]);
break;
case TARGET_NEWLIB_SH_SYS_lseek:
regs[0] = callback->lseek (callback,regs[5], regs[6], regs[7]);
break;
case TARGET_NEWLIB_SH_SYS_close:
regs[0] = callback->close (callback,regs[5]);
break;
case TARGET_NEWLIB_SH_SYS_open:
{
int len = strswaplen (regs[5]);
strnswap (regs[5], len);
regs[0] = callback->open (callback, ptr (regs[5]), regs[6]);
strnswap (regs[5], len);
break;
}
case TARGET_NEWLIB_SH_SYS_exit:
/* EXIT - caller can look in r5 to work out the reason */
raise_exception (SIGQUIT);
regs[0] = regs[5];
break;
case TARGET_NEWLIB_SH_SYS_stat: /* added at hmsi */
/* stat system call */
{
struct stat host_stat;
int buf;
int len = strswaplen (regs[5]);
strnswap (regs[5], len);
regs[0] = stat (ptr (regs[5]), &host_stat);
strnswap (regs[5], len);
buf = regs[6];
WWAT (buf, host_stat.st_dev);
buf += 2;
WWAT (buf, host_stat.st_ino);
buf += 2;
WLAT (buf, host_stat.st_mode);
buf += 4;
WWAT (buf, host_stat.st_nlink);
buf += 2;
WWAT (buf, host_stat.st_uid);
buf += 2;
WWAT (buf, host_stat.st_gid);
buf += 2;
WWAT (buf, host_stat.st_rdev);
buf += 2;
WLAT (buf, host_stat.st_size);
buf += 4;
WLAT (buf, host_stat.st_atime);
buf += 4;
WLAT (buf, 0);
buf += 4;
WLAT (buf, host_stat.st_mtime);
buf += 4;
WLAT (buf, 0);
buf += 4;
WLAT (buf, host_stat.st_ctime);
buf += 4;
WLAT (buf, 0);
buf += 4;
WLAT (buf, 0);
buf += 4;
WLAT (buf, 0);
buf += 4;
}
break;
#ifndef _WIN32