wataash
diff --git a/‎bfd/ChangeLog
+12 b/‎bfd/ChangeLog
+12
diff --git a/‎bfd/archures.c
+9-8 b/‎bfd/archures.c
+9-8
diff --git a/‎bfd/bfd-in2.h
+12-8 b/‎bfd/bfd-in2.h
+12-8
diff --git a/‎bfd/coff-z80.c
+26 b/‎bfd/coff-z80.c
+26
diff --git a/‎bfd/coffcode.h
+2 b/‎bfd/coffcode.h
+2
diff --git a/‎bfd/cpu-z80.c
+2-1 b/‎bfd/cpu-z80.c
+2-1
@@ -1,3 +1,15 @@
+2020-02-07  Sergey Belyashov  <[email protected]>
+
+	PR 25469
+	* archures.c: Add GBZ80 and Z80N machine values.
+	* reloc.c: Add BFD_RELOC_Z80_16_BE.
+	* coff-z80.c: Add support for new reloc.
+	* coffcode.h: Add support for new machine values.
+	* cpu-z80.c: Add support for new machine names.
+	* elf32-z80.c: Add support for new reloc.
+	* bfd-in2.h: Regenerate.
+	* libbfd.h: Regenerate.
+
 2020-02-07  Nick Clifton  <[email protected]>
 
 	PR 23932
 
@@ -504,14 +504,15 @@ DESCRIPTION
 .  bfd_arch_xtensa,    {* Tensilica's Xtensa cores.  *}
 .#define bfd_mach_xtensa	1
 .  bfd_arch_z80,
-.#define bfd_mach_gbz80         0 {* GameBoy Z80 (reduced instruction set) *}
-.#define bfd_mach_z80strict	1 {* Z80 without undocumented opcodes.  *}
-.#define bfd_mach_z180          2 {* Z180: successor with additional instructions, but without halves of ix and iy *}
-.#define bfd_mach_z80		3 {* Z80 with ixl, ixh, iyl, and iyh.  *}
-.#define bfd_mach_ez80_z80      4 {* eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode *}
-.#define bfd_mach_ez80_adl      5 {* eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode *}
-.#define bfd_mach_z80full	7 {* Z80 with all undocumented instructions.  *}
-.#define bfd_mach_r800		11 {* R800: successor with multiplication.  *}
+.#define bfd_mach_z80strict	1 {* Zilog Z80 without undocumented opcodes.  *}
+.#define bfd_mach_z180		2 {* Zilog Z180: successor with additional instructions, but without halves of ix and iy *}
+.#define bfd_mach_z80		3 {* Zilog Z80 with ixl, ixh, iyl, and iyh.  *}
+.#define bfd_mach_ez80_z80	4 {* Zilog eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode *}
+.#define bfd_mach_ez80_adl	5 {* Zilog eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode *}
+.#define bfd_mach_z80n		6 {* Z80N *}
+.#define bfd_mach_z80full	7 {* Zilog Z80 with all undocumented instructions.  *}
+.#define bfd_mach_gbz80		8 {* GameBoy Z80 (reduced instruction set) *}
+.#define bfd_mach_r800		11 {* Ascii R800: successor with multiplication.  *}
 .  bfd_arch_lm32,      {* Lattice Mico32.  *}
 .#define bfd_mach_lm32		1
 .  bfd_arch_microblaze,{* Xilinx MicroBlaze.  *}
 
@@ -1897,14 +1897,15 @@ enum bfd_architecture
   bfd_arch_xtensa,    /* Tensilica's Xtensa cores.  */
 #define bfd_mach_xtensa        1
   bfd_arch_z80,
-#define bfd_mach_gbz80         0 /* GameBoy Z80 (reduced instruction set) */
-#define bfd_mach_z80strict     1 /* Z80 without undocumented opcodes.  */
-#define bfd_mach_z180          2 /* Z180: successor with additional instructions, but without halves of ix and iy */
-#define bfd_mach_z80           3 /* Z80 with ixl, ixh, iyl, and iyh.  */
-#define bfd_mach_ez80_z80      4 /* eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode */
-#define bfd_mach_ez80_adl      5 /* eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode */
-#define bfd_mach_z80full       7 /* Z80 with all undocumented instructions.  */
-#define bfd_mach_r800          11 /* R800: successor with multiplication.  */
+#define bfd_mach_z80strict     1 /* Zilog Z80 without undocumented opcodes.  */
+#define bfd_mach_z180          2 /* Zilog Z180: successor with additional instructions, but without halves of ix and iy */
+#define bfd_mach_z80           3 /* Zilog Z80 with ixl, ixh, iyl, and iyh.  */
+#define bfd_mach_ez80_z80      4 /* Zilog eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode */
+#define bfd_mach_ez80_adl      5 /* Zilog eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode */
+#define bfd_mach_z80n          6 /* Z80N */
+#define bfd_mach_z80full       7 /* Zilog Z80 with all undocumented instructions.  */
+#define bfd_mach_gbz80         8 /* GameBoy Z80 (reduced instruction set) */
+#define bfd_mach_r800          11 /*Ascii R800: Z80 successor with multiplication.  */
   bfd_arch_lm32,      /* Lattice Mico32.  */
 #define bfd_mach_lm32          1
   bfd_arch_microblaze,/* Xilinx MicroBlaze.  */
@@ -5301,6 +5302,9 @@ BFD_RELOC_XTENSA_ASM_EXPAND.  */
 /* Highest 16 bits of multibyte (32 or 24 bit) value.  */
   BFD_RELOC_Z80_WORD1,
 
+/* 16 bit word big endian */
+  BFD_RELOC_Z80_16_BE,
+
 /* DJNZ offset.  */
   BFD_RELOC_Z8K_DISP7,
 
 
@@ -221,6 +221,21 @@ static bfd_howto_type howto_table[] =
      0,			/* src_mask */
      0xffff,		/* dst_mask */
      FALSE),		/* pcrel_offset */
+
+  BFD_HOWTO (BFD_RELOC_Z80_16_BE,
+     R_IMM16BE,		/* type */
+     0,			/* rightshift */
+     1,			/* size (0 = byte, 1 = short, 2 = long) */
+     16,		/* bitsize */
+     FALSE,		/* pc_relative */
+     0,			/* bitpos */
+     complain_overflow_bitfield, /* complain_on_overflow */
+     0,			/* special_function */
+     "r_imm16be",	/* name */
+     FALSE,		/* partial_inplace */
+     0x0000ffff,	/* src_mask */
+     0x0000ffff,	/* dst_mask */
+     FALSE),		/* pcrel_offset */
 };
 
 #define NUM_HOWTOS ARRAY_SIZE (howto_table)
@@ -421,6 +436,17 @@ extra_case (bfd *in_abfd,
 	break;
       }
 
+    case R_IMM16BE:
+      if (reloc->howto->partial_inplace)
+	val += (bfd_get_8 ( in_abfd, data+*src_ptr+0) * 0x100 +
+		bfd_get_8 ( in_abfd, data+*src_ptr+1)) & reloc->howto->src_mask;
+      
+      bfd_put_8 (in_abfd, val >> 8, data + *dst_ptr+0);
+      bfd_put_8 (in_abfd, val, data + *dst_ptr+1);
+      (*dst_ptr) += 2;
+      (*src_ptr) += 2;
+      break;
+
     default:
       abort ();
     }
 
@@ -2163,6 +2163,7 @@ coff_set_arch_mach_hook (bfd *abfd, void * filehdr)
 	{
 	case bfd_mach_z80strict << 12:
 	case bfd_mach_z80 << 12:
+	case bfd_mach_z80n << 12:
 	case bfd_mach_z80full << 12:
 	case bfd_mach_r800 << 12:
 	case bfd_mach_gbz80 << 12:
@@ -2655,6 +2656,7 @@ coff_set_flags (bfd * abfd,
 	{
 	case bfd_mach_z80strict:
 	case bfd_mach_z80:
+	case bfd_mach_z80n:
 	case bfd_mach_z80full:
 	case bfd_mach_r800:
 	case bfd_mach_gbz80:
 
@@ -54,7 +54,8 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (bfd_mach_r800,	 "r800",       16, FALSE, M(4)),
   N (bfd_mach_gbz80,	 "gbz80",      16, FALSE, M(5)),
   N (bfd_mach_z180,	 "z180",       16, FALSE, M(6)),
-  N (bfd_mach_ez80_z80,	 "ez80-z80",   16, FALSE, M(7)),
+  N (bfd_mach_z80n,	 "z80n",       16, FALSE, M(7)),
+  N (bfd_mach_ez80_z80,	 "ez80-z80",   16, FALSE, M(8)),
   N (bfd_mach_ez80_adl,	 "ez80-adl",   24, FALSE, NULL)
 };