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Computer-Science-Textbooks Public
Forked from kaitoukito/Computer-Science-TextbooksCollect some CS textbooks for learning.
UpdatedApr 14, 2024 -
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My-RISCV64-CORE-writing Public
一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
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RV64-ISA-book Public
是RV64各指令的解释，简体中文。RV64's inst description . Simple chinese.
1 UpdatedJun 15, 2022 -
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rocket-chip Public
Forked from chipsalliance/rocket-chipRocket Chip Generator
Scala Other UpdatedMay 19, 2022 -
All-of-SystemVerilog Public
Forked from vengineer-systemverilog/All-of-SystemVerilogみんなのSystemVerilog
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SOL-s-Verilog-Cheatsheet-for-Not-So-Beginners Public
Forked from ProjectDimlight/SOL-s-Verilog-Cheatsheet-for-Not-So-BeginnersApache License 2.0 UpdatedMay 10, 2022 -
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pygears Public
Forked from bogdanvuk/pygearsHW Design: A Functional Approach
Python MIT License UpdatedMar 16, 2022 -
riscv-boom Public
Forked from riscv-boom/riscv-boomSonicBOOM: The Berkeley Out-of-Order Machine
Scala BSD 3-Clause "New" or "Revised" License UpdatedMar 11, 2022 -
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ritter-soc Public
Forked from tastynoob/ritter-soca 4-pipeline riscv soc , based with rv32im ,designed by verilog
Verilog GNU General Public License v3.0 UpdatedMar 7, 2022 -
riscv-mini Public
Forked from ucb-bar/riscv-miniSimple RISC-V 3-stage Pipeline in Chisel
Scala Other UpdatedMar 3, 2022 -
NutShell Public
Forked from OSCPU/NutShellRISC-V SoC designed by students in UCAS
Scala Other UpdatedMar 2, 2022 -
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KyogenRV Public
Forked from panda5mt/KyogenRVThe Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
Scala Apache License 2.0 UpdatedApr 11, 2021 -
homemade-riscv Public
Forked from horie-t/homemade-riscv『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
Scala BSD 3-Clause "New" or "Revised" License UpdatedJul 30, 2019 -
computer-systems-ucas Public
Forked from sailordiary/computer-systems-ucas中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
Verilog UpdatedJun 24, 2017