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Commits on Jan 15, 2014

• replace strdup() with our cs_strdup(), which call cs_mem_malloc() internally

  aquynh

  committed
  a9ffb44

• python: update Cython for the change on @op_str in the core

  aquynh

  committed
  fc947e0

• python & java: update following the last change to @op_str

  aquynh

  committed
  9eb9f53

• increase size of @op_str to 160 to contain long operand string of some Neon Arm instructions

  aquynh

  committed
  0636f68

• ppc: replace constant subtarget numbers with macros

  aquynh

  committed
  57c50d4

• x86: some arithmetic instructions should not update accumulate registers

  aquynh

  committed
  136e2df

• arm: update core

  aquynh

  committed
  9cc56a3

• suite: make all tests consistenly run from inside suite/

  aquynh

  committed
  d8029ae

• arm64: update core

  aquynh

  committed
  cbb10ba

• add some comments on the availability of some APIs relying on detail = ON

  aquynh

  committed
  2f05ab2

Commits on Jan 14, 2014

• java: update Mips constants following the change in Mips' core

  aquynh

  committed
  0941042

• python: update Mips constants following the change in Mips' core

  aquynh

  committed
  a4e6e2a

• mips: update core

  aquynh

  committed
  75ef242

• python & java: pump API to 2.0

  aquynh

  committed
  44cebf2

Commits on Jan 13, 2014

• x86: few more SUB insn should not affect accumulate register

  aquynh

  committed
  9c2d029

• extend @op_str of cs_insn_flat following the core change

  aquynh

  committed
  3d56b82

• x86: some ADD & SUB insn should not affect accumulate registers. bug reported by Bleh

  aquynh

  committed
  22800aa

• python: fix Cython binding following the latest core change on @op_str

  aquynh

  committed
  7900458

• java: update @opstr & ARM's @operands following the changes in core

  aquynh

  committed
  a71a299

• python: update @op_str & ARM's @operands following the changes in core

  aquynh

  committed
  e03da92

• increase sizes of @op_str & ARM @operands to contain some ARM instructions with super long list of registers. issue reported by Deroko of ARTeam

  aquynh

  committed
  b99aec8

• python: indentation for cython code. also added author credits to these new files

  aquynh

  committed
  a84fe66

• python: update clean target for *.pyx files

  aquynh

  committed
  aaaf345

• update .gitignore for new *.pyx files generated by cython

  aquynh

  committed
  2fcfeac

• Clean up addition cython code

  danghvu

  committed
  e61c504

• Improve cython by using CCsInsn when possible

  danghvu

  committed
  cfd41dd

• suite: benchmark.py can benchmark specific archs, rather than all archs like before

  aquynh

  committed
  f48a879

• suite: benchmark.py now exercises all archs

  aquynh

  committed
  783e6c0

• suite: excercise benchmark.py 5 times more

  aquynh

  committed
  ff93d75

• suite: benchmark.py get disasm code from binary file (python itself) rather than randomize data - this stablizes results, and can be compared with other bindings

  aquynh

  committed
  34474f8

• python: generator yields nothing rather than [] on failure

  aquynh

  committed
  e14556a

• some minor fixes for config.mk

  aquynh

  committed
  cf4df4b

Commits on Jan 12, 2014

• ppc & x86: add third dummy MRI argument to printInstruction() to make it consistent with other archs

  aquynh

  committed
  e51e227

• mips: printInstruction() is static function. add dummy third argument MRI to be consistent with other archs

  aquynh

  committed
  56774a1

• arm64: find alias insn after the main isnn name mapping.

  aquynh

  committed
  dcbe0f8

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