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[Sparc] Add VIS instructions to sparc backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202660 91177308-0d34-0410-b5e6-96231b3b80d8
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+294
-8
lines changed

5 files changed

+294
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lines changed

‎lib/Target/Sparc/Sparc.td

+17-6
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,12 @@ def FeatureV8Deprecated
2929
def FeatureVIS
3030
: SubtargetFeature<"vis", "IsVIS", "true",
3131
"Enable UltraSPARC Visual Instruction Set extensions">;
32+
def FeatureVIS2
33+
: SubtargetFeature<"vis2", "IsVIS2", "true",
34+
"Enable Visual Instruction Set extensions II">;
35+
def FeatureVIS3
36+
: SubtargetFeature<"vis3", "IsVIS3", "true",
37+
"Enable Visual Instruction Set extensions III">;
3238

3339
def FeatureHardQuad
3440
: SubtargetFeature<"hard-quad-float", "HasHardQuad", "true",
@@ -69,12 +75,17 @@ def : Proc<"sparclite86x", []>;
6975
def : Proc<"sparclet", []>;
7076
def : Proc<"tsc701", []>;
7177
def : Proc<"v9", [FeatureV9]>;
72-
def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated]>;
73-
def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated]>;
74-
def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated]>;
75-
def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc]>;
76-
def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc]>;
77-
def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc]>;
78+
def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
79+
def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
80+
FeatureVIS2]>;
81+
def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
82+
FeatureVIS2]>;
83+
def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc,
84+
FeatureVIS, FeatureVIS2]>;
85+
def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc,
86+
FeatureVIS, FeatureVIS2]>;
87+
def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,
88+
FeatureVIS, FeatureVIS2, FeatureVIS3]>;
7889

7990

8091
//===----------------------------------------------------------------------===//

‎lib/Target/Sparc/SparcInstrInfo.td

+7-1
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,12 @@ def HasV9 : Predicate<"Subtarget.isV9()">,
3838
def HasNoV9 : Predicate<"!Subtarget.isV9()">;
3939

4040
// HasVIS - This is true when the target processor has VIS extensions.
41-
def HasVIS : Predicate<"Subtarget.isVIS()">;
41+
def HasVIS : Predicate<"Subtarget.isVIS()">,
42+
AssemblerPredicate<"FeatureVIS">;
43+
def HasVIS2 : Predicate<"Subtarget.isVIS2()">,
44+
AssemblerPredicate<"FeatureVIS2">;
45+
def HasVIS3 : Predicate<"Subtarget.isVIS3()">,
46+
AssemblerPredicate<"FeatureVIS3">;
4247

4348
// HasHardQuad - This is true when the target processor supports quad floating
4449
// point instructions.
@@ -1184,4 +1189,5 @@ def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
11841189

11851190

11861191
include "SparcInstr64Bit.td"
1192+
include "SparcInstrVIS.td"
11871193
include "SparcInstrAliases.td"

‎lib/Target/Sparc/SparcInstrVIS.td

+263
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,263 @@
1+
//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===//
2+
//
3+
// The LLVM Compiler Infrastructure
4+
//
5+
// This file is distributed under the University of Illinois Open Source
6+
// License. See LICENSE.TXT for details.
7+
//
8+
//===----------------------------------------------------------------------===//
9+
//
10+
// This file contains instruction formats, definitions and patterns needed for
11+
// VIS, VIS II, VIS II instructions on SPARC.
12+
//===----------------------------------------------------------------------===//
13+
14+
// VIS Instruction Format.
15+
class VISInstFormat<bits<9> opfval, dag outs, dag ins, string asmstr,
16+
list<dag> pattern>
17+
: F3_3<0b10, 0b110110, opfval, outs, ins, asmstr, pattern>;
18+
19+
class VISInst<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
20+
: VISInstFormat<opfval,
21+
(outs RC:$rd), (ins RC:$rs1, RC:$rs2),
22+
!strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
23+
24+
// VIS Instruction with integer destination register.
25+
class VISInstID<bits<9> opfval, string OpcStr>
26+
: VISInstFormat<opfval,
27+
(outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
28+
!strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
29+
30+
// For VIS Instructions with no operand.
31+
let rd = 0, rs1 = 0, rs2 = 0 in
32+
class VISInst0<bits<9> opfval, string asmstr>
33+
: VISInstFormat<opfval, (outs), (ins), asmstr, []>;
34+
35+
// For VIS Instructions with only rs1, rd operands.
36+
let rs2 = 0 in
37+
class VISInst1<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
38+
: VISInstFormat<opfval,
39+
(outs RC:$rd), (ins RC:$rs1),
40+
!strconcat(OpcStr, " $rs1, $rd"), []>;
41+
42+
// For VIS Instructions with only rs2, rd operands.
43+
let rs1 = 0 in
44+
class VISInst2<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
45+
: VISInstFormat<opfval,
46+
(outs RC:$rd), (ins RC:$rs2),
47+
!strconcat(OpcStr, " $rs2, $rd"), []>;
48+
49+
// For VIS Instructions with only rd operand.
50+
let Constraints = "$rd = $f", rs1 = 0, rs2 = 0 in
51+
class VISInstD<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
52+
: VISInstFormat<opfval,
53+
(outs RC:$rd), (ins RC:$f),
54+
!strconcat(OpcStr, " $rd"), []>;
55+
56+
// VIS 1 Instructions
57+
let Predicates = [HasVIS] in {
58+
59+
def FPADD16 : VISInst<0b001010000, "fpadd16">;
60+
def FPADD16S : VISInst<0b001010001, "fpadd16s">;
61+
def FPADD32 : VISInst<0b001010010, "fpadd32">;
62+
def FPADD32S : VISInst<0b001010011, "fpadd32s">;
63+
def FPSUB16 : VISInst<0b001010100, "fpsub16">;
64+
def FPSUB16S : VISInst<0b001010101, "fpsub16S">;
65+
def FPSUB32 : VISInst<0b001010110, "fpsub32">;
66+
def FPSUB32S : VISInst<0b001010111, "fpsub32S">;
67+
68+
def FPACK16 : VISInst2<0b000111011, "fpack16">;
69+
def FPACK32 : VISInst <0b000111010, "fpack32">;
70+
def FPACKFIX : VISInst2<0b000111101, "fpackfix">;
71+
def FEXPAND : VISInst2<0b001001101, "fexpand">;
72+
def FPMERGE : VISInst <0b001001011, "fpmerge">;
73+
74+
def FMUL8X16 : VISInst<0b00110001, "fmul8x16">;
75+
def FMUL8X16AU : VISInst<0b00110011, "fmul8x16au">;
76+
def FMUL8X16AL : VISInst<0b00110101, "fmul8x16al">;
77+
def FMUL8SUX16 : VISInst<0b00110110, "fmul8sux16">;
78+
def FMUL8ULX16 : VISInst<0b00110111, "fmul8ulx16">;
79+
def FMULD8SUX16 : VISInst<0b00111000, "fmuld8sux16">;
80+
def FMULD8ULX16 : VISInst<0b00111001, "fmuld8ulx16">;
81+
82+
def ALIGNADDR : VISInst<0b000011000, "alignaddr", I64Regs>;
83+
def ALIGNADDRL : VISInst<0b000011010, "alignaddrl", I64Regs>;
84+
def FALIGNADATA : VISInst<0b001001000, "faligndata">;
85+
86+
def FZERO : VISInstD<0b001100000, "fzero">;
87+
def FZEROS : VISInstD<0b001100001, "fzeros", FPRegs>;
88+
def FONE : VISInstD<0b001111110, "fone">;
89+
def FONES : VISInstD<0b001111111, "fones", FPRegs>;
90+
def FSRC1 : VISInst1<0b001110100, "fsrc1">;
91+
def FSRC1S : VISInst1<0b001110101, "fsrc1s", FPRegs>;
92+
def FSRC2 : VISInst2<0b001111000, "fsrc2">;
93+
def FSRC2S : VISInst2<0b001111001, "fsrc2s", FPRegs>;
94+
def FNOT1 : VISInst1<0b001101010, "fnot1">;
95+
def FNOT1S : VISInst1<0b001101011, "fnot1s", FPRegs>;
96+
def FNOT2 : VISInst2<0b001100110, "fnot2">;
97+
def FNOT2S : VISInst2<0b001100111, "fnot2s", FPRegs>;
98+
def FOR : VISInst<0b001111100, "for">;
99+
def FORS : VISInst<0b001111101, "fors", FPRegs>;
100+
def FNOR : VISInst<0b001100010, "fnor">;
101+
def FNORS : VISInst<0b001100011, "fnors", FPRegs>;
102+
def FAND : VISInst<0b001110000, "fand">;
103+
def FANDS : VISInst<0b001110001, "fands", FPRegs>;
104+
def FNAND : VISInst<0b001101110, "fnand">;
105+
def FNANDS : VISInst<0b001101111, "fnands", FPRegs>;
106+
def FXOR : VISInst<0b001101100, "fxor">;
107+
def FXORS : VISInst<0b001101101, "fxors", FPRegs>;
108+
def FXNOR : VISInst<0b001110010, "fxnor">;
109+
def FXNORS : VISInst<0b001110011, "fxnors", FPRegs>;
110+
111+
def FORNOT1 : VISInst<0b001111010, "fornot1">;
112+
def FORNOT1S : VISInst<0b001111011, "fornot1s", FPRegs>;
113+
def FORNOT2 : VISInst<0b001110110, "fornot2">;
114+
def FORNOT2S : VISInst<0b001110111, "fornot2s", FPRegs>;
115+
def FANDNOT1 : VISInst<0b001101000, "fandnot1">;
116+
def FANDNOT1S : VISInst<0b001101001, "fandnot1s", FPRegs>;
117+
def FANDNOT2 : VISInst<0b001100100, "fandnot2">;
118+
def FANDNOT2S : VISInst<0b001100101, "fandnot2s", FPRegs>;
119+
120+
def FCMPGT16 : VISInstID<0b000101000, "fcmpgt16">;
121+
def FCMPGT32 : VISInstID<0b000101100, "fcmpgt32">;
122+
def FCMPLE16 : VISInstID<0b000100000, "fcmple16">;
123+
def FCMPLE32 : VISInstID<0b000100100, "fcmple32">;
124+
def FCMPNE16 : VISInstID<0b000100010, "fcmpne16">;
125+
def FCMPNE32 : VISInstID<0b000100110, "fcmpne32">;
126+
def FCMPEQ16 : VISInstID<0b000101010, "fcmpeq16">;
127+
def FCMPEQ32 : VISInstID<0b000101110, "fcmpeq32">;
128+
129+
130+
def EDGE8 : VISInst<0b000000000, "edge8", I64Regs>;
131+
def EDGE8L : VISInst<0b000000010, "edge8l", I64Regs>;
132+
def EDGE16 : VISInst<0b000000100, "edge16", I64Regs>;
133+
def EDGE16L : VISInst<0b000000110, "edge16l", I64Regs>;
134+
def EDGE32 : VISInst<0b000001000, "edge32", I64Regs>;
135+
def EDGE32L : VISInst<0b000001010, "edge32l", I64Regs>;
136+
137+
def PDIST : VISInst<0b00111110, "pdist">;
138+
139+
def ARRAY8 : VISInst<0b000010000, "array8", I64Regs>;
140+
def ARRAY16 : VISInst<0b000010010, "array16", I64Regs>;
141+
def ARRAY32 : VISInst<0b000010100, "array32", I64Regs>;
142+
143+
def SHUTDOWN : VISInst0<0b010000000, "shutdown">;
144+
145+
} // Predicates = [HasVIS]
146+
147+
148+
// VIS 2 Instructions.
149+
let Predicates = [HasVIS2] in {
150+
151+
def BMASK : VISInst<0b000011001, "bmask", I64Regs>;
152+
def BSHUFFLE : VISInst<0b000011100, "bshuffle">;
153+
154+
def SIAM : VISInst0<0b010000001, "siam">;
155+
156+
def EDGE8N : VISInst<0b000000001, "edge8n", I64Regs>;
157+
def EDGE8LN : VISInst<0b000000011, "edge8ln", I64Regs>;
158+
def EDGE16N : VISInst<0b000000101, "edge16n", I64Regs>;
159+
def EDGE16LN : VISInst<0b000000111, "edge16ln", I64Regs>;
160+
def EDGE32N : VISInst<0b000001001, "edge32n", I64Regs>;
161+
def EDGE32LN : VISInst<0b000001011, "edge32ln", I64Regs>;
162+
} // Predicates = [HasVIS2]
163+
164+
165+
// VIS 3 Instructions.
166+
let Predicates = [HasVIS3] in {
167+
168+
let Uses = [ICC] in
169+
def ADDXC : VISInst<0b000010001, "addxc", I64Regs>;
170+
171+
let Defs = [ICC], Uses = [ICC] in
172+
def ADDXCCC : VISInst<0b000010011, "addxccc", I64Regs>;
173+
174+
let rd = 0, rs1 = 0 in {
175+
def CMASK8 : VISInstFormat<0b000011011, (outs), (ins I64Regs:$rs2),
176+
"cmask8 $rs2", []>;
177+
def CMASK16 : VISInstFormat<0b000011101, (outs), (ins I64Regs:$rs2),
178+
"cmask16 $rs2", []>;
179+
def CMASK32 : VISInstFormat<0b000011111, (outs), (ins I64Regs:$rs2),
180+
"cmask32 $rs2", []>;
181+
182+
}
183+
184+
def FCHKSM16 : VISInst<0b01000100, "fchksm16">;
185+
186+
def FHADDS : F3_3<0b10, 0b110100, 0b001100001,
187+
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
188+
"fhadds $rs1, $rs2, $rd", []>;
189+
def FHADDD : F3_3<0b10, 0b110100, 0b001100010,
190+
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
191+
"fhaddd $rs1, $rs2, $rd", []>;
192+
def FHSUBS : F3_3<0b10, 0b110100, 0b001100101,
193+
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
194+
"fhsubs $rs1, $rs2, $rd", []>;
195+
def FHSUBD : F3_3<0b10, 0b110100, 0b001100110,
196+
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
197+
"fhsubd $rs1, $rs2, $rd", []>;
198+
def FLCMPS : VISInstFormat<0b101010001, (outs FCCRegs:$rd),
199+
(ins DFPRegs:$rs1, DFPRegs:$rs2),
200+
"flcmps $rd, $rs1, $rs2", []>;
201+
def FLCMPD : VISInstFormat<0b101010010, (outs FCCRegs:$rd),
202+
(ins DFPRegs:$rs1, DFPRegs:$rs2),
203+
"flcmpd $rd, $rs1, $rs2", []>;
204+
205+
def FMEAN16 : VISInst<0b001000000, "fmean16">;
206+
207+
def FNADDS : F3_3<0b10, 0b110100, 0b001010001,
208+
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
209+
"fnadds $rs1, $rs2, $rd", []>;
210+
def FNADDD : F3_3<0b10, 0b110100, 0b001010010,
211+
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
212+
"fnaddd $rs1, $rs2, $rd", []>;
213+
def FNHADDS : F3_3<0b10, 0b110100, 0b001110001,
214+
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
215+
"fnhadds $rs1, $rs2, $rd", []>;
216+
def FNHADDD : F3_3<0b10, 0b110100, 0b001110010,
217+
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
218+
"fnhaddd $rs1, $rs2, $rd", []>;
219+
220+
def FNMULS : F3_3<0b10, 0b110100, 0b001011001,
221+
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
222+
"fnhadds $rs1, $rs2, $rd", []>;
223+
def FNMULD : F3_3<0b10, 0b110100, 0b001011010,
224+
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
225+
"fnhaddd $rs1, $rs2, $rd", []>;
226+
def FNSMULD : F3_3<0b10, 0b110100, 0b001111001,
227+
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
228+
"fnhadds $rs1, $rs2, $rd", []>;
229+
230+
def FPADD64 : VISInst<0b001000010, "fpadd64">;
231+
232+
def FSLL16 : VISInst<0b00100001, "fsll16">;
233+
def FSRL16 : VISInst<0b00100011, "fsrl16">;
234+
def FSLL32 : VISInst<0b00100101, "fsll32">;
235+
def FSRL32 : VISInst<0b00100111, "fsrl32">;
236+
def FSLAS16 : VISInst<0b00101001, "fslas16">;
237+
def FSRA16 : VISInst<0b00101011, "fsra16">;
238+
def FSLAS32 : VISInst<0b00101101, "fslas32">;
239+
def FSRA32 : VISInst<0b00101111, "fsra32">;
240+
241+
let rs1 = 0 in
242+
def LZCNT : VISInstFormat<0b000010111, (outs I64Regs:$rd),
243+
(ins I64Regs:$rs2), "lzcnt $rs2, $rd", []>;
244+
245+
let rs1 = 0 in {
246+
def MOVSTOSW : VISInstFormat<0b100010011, (outs I64Regs:$rd),
247+
(ins DFPRegs:$rs2), "movstosw $rs2, $rd", []>;
248+
def MOVSTOUW : VISInstFormat<0b100010001, (outs I64Regs:$rd),
249+
(ins DFPRegs:$rs2), "movstouw $rs2, $rd", []>;
250+
def MOVDTOX : VISInstFormat<0b100010000, (outs I64Regs:$rd),
251+
(ins DFPRegs:$rs2), "movdtox $rs2, $rd", []>;
252+
def MOVWTOS : VISInstFormat<0b100011001, (outs DFPRegs:$rd),
253+
(ins I64Regs:$rs2), "movdtox $rs2, $rd", []>;
254+
def MOVXTOD : VISInstFormat<0b100011000, (outs DFPRegs:$rd),
255+
(ins I64Regs:$rs2), "movdtox $rs2, $rd", []>;
256+
}
257+
258+
def PDISTN : VISInst<0b000111111, "pdistn">;
259+
260+
def UMULXHI : VISInst<0b000010110, "umulxhi", I64Regs>;
261+
def XMULX : VISInst<0b100010101, "xmulx", I64Regs>;
262+
def XMULXHI : VISInst<0b100010111, "xmulxhi", I64Regs>;
263+
} // Predicates = [IsVIS3]

‎lib/Target/Sparc/SparcSubtarget.h

+3-1
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
2727
virtual void anchor();
2828
bool IsV9;
2929
bool V8DeprecatedInsts;
30-
bool IsVIS;
30+
bool IsVIS, IsVIS2, IsVIS3;
3131
bool Is64Bit;
3232
bool HasHardQuad;
3333
bool UsePopc;
@@ -38,6 +38,8 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
3838

3939
bool isV9() const { return IsV9; }
4040
bool isVIS() const { return IsVIS; }
41+
bool isVIS2() const { return IsVIS2; }
42+
bool isVIS3() const { return IsVIS3; }
4143
bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; }
4244
bool hasHardQuad() const { return HasHardQuad; }
4345
bool usePopc() const { return UsePopc; }

‎test/MC/Sparc/sparc-vis.s

+4
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
! RUN: llvm-mc %s -arch=sparcv9 -mcpu=niagara -show-encoding | FileCheck %s
2+
3+
! CHECK: fzeros %f31 ! encoding: [0xbf,0xb0,0x0c,0x20]
4+
fzeros %f31

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