forked from xiaop1/Verilog-Practice
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy path130_Lemmings2.v
64 lines (59 loc) · 1.65 KB
/
130_Lemmings2.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah );
parameter LEFT = 0, RIGHT = 1, LEFT_aah = 2, RIGHT_aah = 3;
reg [2:0] state, next_state;
always @(posedge clk or posedge areset) begin
if (areset) begin
state <= LEFT;
end
else begin
state <= next_state;
end
end
always @(*) begin
case (state)
LEFT: begin
if (ground) begin
next_state <= bump_left ? RIGHT : LEFT;
end
else begin
next_state <= LEFT_aah;
end
end
RIGHT: begin
if (ground) begin
next_state <= bump_right ? LEFT : RIGHT;
end
else begin
next_state <= RIGHT_aah;
end
end
LEFT_aah: begin
if (ground) begin
next_state <= LEFT;
end
else begin
next_state <= LEFT_aah;
end
end
RIGHT_aah: begin
if (ground) begin
next_state <= RIGHT;
end
else begin
next_state <= RIGHT_aah;
end
end
endcase
end
assign walk_left = (state == LEFT);
assign walk_right = (state == RIGHT);
assign aaah = ((state == LEFT_aah) || (state == RIGHT_aah));
endmodule