Skip to content

Latest commit

 

History

History
49 lines (35 loc) · 1.95 KB

Simple-Hardware-Adder_-The-Adder.md

File metadata and controls

49 lines (35 loc) · 1.95 KB

Back | Next | Contents
My First SoC - Simple Hardware Adder

Simple Adder

Summary

Here we create a simple adder module. While the adder is quite simple, there is one important thing to take note of. We are creating a regular adder in verilog which would be just how you would have designed it if you were going to use it in a simple FPGA and not an SoC. This demonstrates how you can take an existing design that works in an FPGA and re-use it in an SoC. Pretty cool stuff!

Simple Adder module

This is as easy as can be. We're going to design a 64 bit adder. It will take 2 64 bit inputs and return a 64 bit output:

module simple_adder(
  input logic [63:0] a,
  input logic [63:0] b,
  output logic [63:0] sum
);
assign sum = a + b;

endmodule

Save this in a folder in your working directory:

cd $DEWD
mkdir -p ip/simple_adder
cd ip/simple_adder
vim simple_adder.sv
# Paste the code here and save

This completes the adder. Use the menu on the right to go to the next section.

Next | Primer on Avalon MM
Back | Initial project setup

My First SoC - Simple Hardware Adder | Table of Contents