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Commits on Sep 10, 2018

• Include RVC pseudos in chisel decoder

  aswaterman

  committed
  e24529d

Commits on Aug 25, 2018

• Improve TeX output for FENCE instructions

  aswaterman

  committed
  7c2474e

Commits on Aug 6, 2018

• FENCE has a field called FM in bits 31:28

  aswaterman

  committed
  7dd3b0e

Commits on Jul 17, 2018

• Make the hashbang portable (riscv#20)

  Show description for 3aa3206
  

  trasz

  authored and

  aswaterman

  committed
  3aa3206

Commits on Apr 25, 2018

• Add proposed FENCE.TSO encoding

  aswaterman

  committed
  c13a759

Commits on Dec 27, 2017

• Use old C style comments. (riscv#18)

  Show description for 25881d8
  

  timsifive

  authored and

  aswaterman

  committed
  25881d8

Commits on Nov 27, 2017

• Rename sptbr to satp and sbadaddr to stval

  Show description for 7c3db43
  aswaterman

  committed
  7c3db43

• Don't copy encoding.h to binutils anymore

  Show description for 32071f8
  aswaterman

  committed
  32071f8

• Generate encoding.h for OpenOCD as well. (riscv#16)

  

  timsifive

  authored and

  aswaterman

  committed
  58b6f41

Commits on May 17, 2017

• Merge remote-tracking branch 'origin/priv-1.10'

  palmer-dabbelt

  committed
  e0abc22

Commits on May 8, 2017

• SB->B; UJ->J

  aswaterman

  committed
  f8bab12

• Add UXl/SXL

  aswaterman

  committed
  1ac9833

Commits on Apr 25, 2017

• Add ECALL/EBREAK to privileged instruction table

  aswaterman

  committed
  18383e7

• FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X

  aswaterman

  committed
  228c474

• Remove hret instruction

  aswaterman

  committed
  03c186e

Commits on Mar 31, 2017

• Add LICENSE

  aswaterman

  committed
  4b62298

• Support generating Go code (riscv#3)

  Show description for f86f5cb
  

  bbarenblat

  authored and

  aswaterman

  committed
  f86f5cb

Commits on Mar 30, 2017

• New PMP encoding

  aswaterman

  committed
  e4c9357

Commits on Mar 27, 2017

• Separate page faults from physical memory access exceptions

  aswaterman

  committed
  d86c50a

Commits on Mar 23, 2017

• Add PMP

  aswaterman

  committed
  771cd8a

• Add TW/TVM/TSR fields to mstatus

  aswaterman

  committed
  ec5a822

Commits on Mar 9, 2017

• New counter-enable mechanism

  aswaterman

  committed
  2536e52

• Update SPTBR fields

  aswaterman

  committed
  b6747a2

Commits on Feb 21, 2017

• Use gcc csr register constraint

  aswaterman

  committed
  282321b

• Remove sfence.vm and add sfence.vma

  aswaterman

  committed
  ee4249c

• Drop mstatus.VM field

  aswaterman

  committed
  689c591

Commits on Feb 15, 2017

• Don't update binutils' riscv-opc.h automatically anymore

  Show description for 03a7a33
  aswaterman

  committed
  03a7a33

Commits on Feb 8, 2017

• Encode VM type in sptbr, not mstatus

  Show description for cd10c71
  aswaterman

  committed
  cd10c71

Commits on Dec 21, 2016

• Add Q extension

  

  kito-cheng

  authored and

  aswaterman

  committed
  3c1a911

• Fix first line of riscv-opc.h, gnu coding style need end with 1 dot and 2 space

  

  kito-cheng

  authored and

  aswaterman

  committed
  5f5c591

Commits on Dec 7, 2016

• avoid non-standard predefined macros

  aswaterman

  committed
  7650b39

Commits on Aug 27, 2016

• Renumber misa; add performance counter CSRs

  

  Andrew Waterman

  committed
  c86d2ee

• Add mcontrol type constants. (riscv#11)

  

  timsifive

  authored and

  aswaterman

  committed
  9f3e389

Commits on Aug 26, 2016

• Re-rename trigger registers to be 1-based

  

  Andrew Waterman

  committed
  7d22c88

Commits on Aug 25, 2016

• Make hardware triggers match latest spec.

  

  timsifive

  authored and

  Andrew Waterman

  committed
  1a25601

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