xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done

Don't set TX FIFO UNDERFLOW interrupt after transmitting the commands. Also update interrupts after reading out the interrupt status. Signed-off-by: Francisco Iglesias <[email protected]> Acked-by: Alistair Francis <[email protected]> Reviewed-by: Edgar E. Iglesias <[email protected]> Tested-by: Edgar E. Iglesias <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
0x3h · Dec 13, 2017 · 2e1cf2c · 2e1cf2c
1 parent fbfaa50
commit 2e1cf2c
Showing 1 changed file with 1 addition and 3 deletions.
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
@@ -329,9 +329,6 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
         uint8_t addr_length;
 
         if (fifo8_is_empty(&s->tx_fifo)) {
-            if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
-                s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
-            }
             xilinx_spips_update_ixr(s);
             return;
         } else if (s->snoop_state == SNOOP_STRIPING) {
@@ -530,6 +527,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
         ret = s->regs[addr] & IXR_ALL;
         s->regs[addr] = 0;
         DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
+        xilinx_spips_update_ixr(s);
         return ret;
     case R_INTR_MASK:
         mask = IXR_ALL;