comment and TODO cleanup

1donavan · Jan 15, 2020 · ef9dfb2 · ef9dfb2
1 parent 77ca585
commit ef9dfb2
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Showing 3 changed files with 3 additions and 51 deletions.
diff --git a/bp_me/src/v/cce/bp_cce.v b/bp_me/src/v/cce/bp_cce.v
@@ -67,16 +67,6 @@ module bp_cce
    , input                                             mem_cmd_ready_i
   );
 
-  /*
-  //synopsys translate_off
-  initial begin
-    assert (lce_sets_p > 1) else $error("Number of LCE sets must be greater than 1");
-    assert (num_cce_p >= 1 && `BSG_IS_POW2(num_cce_p))
-      else $error("Number of CCE must be power of two");
-  end
-  //synopsys translate_on
-  */
-
   // Define structure variables for output queues
 
   `declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p);
@@ -299,12 +289,10 @@ module bp_cce
       ,.num_lce_p(num_lce_p)
       ,.lce_assoc_p(lce_assoc_p)
       ,.tag_width_p(tag_width_lp)
-      ,.cce_id_width_p(cce_id_width_p)
       )
     directory
      (.clk_i(clk_i)
       ,.reset_i(reset_i)
-      ,.cce_id_i(cfg_bus_cast_i.cce_id)
 
       ,.set_i(dir_set_li[0+:lg_num_way_groups_lp])
       ,.lce_i(dir_lce_li)

diff --git a/bp_me/src/v/cce/bp_cce_dir.v b/bp_me/src/v/cce/bp_cce_dir.v
@@ -44,6 +44,7 @@ module bp_cce_dir
 
     // Number of rows to hold one set from all LCEs
     // TODO: this wastes space if there is an odd number of LCEs in the system
+    // since tag_sets_per_row_lp is hard-coded to 2.
     , localparam rows_per_set_lp          = (num_lce_p == 1) ? 1
                                             :((num_lce_p % tag_sets_per_row_lp) == 0)
                                               ? (num_lce_p / tag_sets_per_row_lp)
@@ -67,9 +68,6 @@ module bp_cce_dir
     , localparam lg_rows_lp               = `BSG_SAFE_CLOG2(rows_lp)
 
     , localparam addr_offset_shift_lp     = 1
-
-    // TODO: DEBUG only
-    , parameter cce_id_width_p            = "inv"
   )
   (input                                                          clk_i
    , input                                                        reset_i
@@ -85,7 +83,7 @@ module bp_cce_dir
    , input [$bits(bp_coh_states_e)-1:0]                           coh_state_i
    , input [`bp_cce_inst_minor_op_width-1:0]                      w_cmd_i
    , input                                                        w_v_i
-   // TODO: fix this input functionality?
+   // TODO: this is used by FSM CCE, but not ucode CCE currently
    , input                                                        w_clr_row_i
 
    , output logic                                                 busy_o
@@ -100,9 +98,6 @@ module bp_cce_dir
    , output logic [tag_width_p-1:0]                               lru_tag_o
 
    , output logic [tag_width_p-1:0]                               tag_o
-
-   // TODO: debug only, remove
-   , input [cce_id_width_p-1:0]                                   cce_id_i
   );
 
   initial begin
@@ -122,8 +117,7 @@ module bp_cce_dir
     end
   endgenerate
   wire [lg_num_lce_lp-1:0] addr_lce = (lce_i >> addr_offset_shift_lp);
-  wire [lg_rows_lp-1:0] addr_offset;
-  assign addr_offset = addr_offset_table[addr_lce[0+:lg_rows_per_set_lp]];
+  wire [lg_rows_lp-1:0] addr_offset = addr_offset_table[addr_lce[0+:lg_rows_per_set_lp]];
 
   // directory address for single entry operations
   wire [lg_rows_lp-1:0] entry_row_addr = addr_offset + set_i;
@@ -182,21 +176,6 @@ module bp_cce_dir
   logic [tag_sets_per_row_lp-1:0][lg_lce_assoc_lp-1:0]            sharers_ways;
   logic [tag_sets_per_row_lp-1:0][$bits(bp_coh_states_e)-1:0]     sharers_coh_states;
 
-  // TODO: debug, remove
-  /*
-  always_ff @(negedge clk_i) begin
-    if (~reset_i) begin
-      if (w_v_i) begin
-        $display("[%t] CCE[%d] write WG[%d] ramAddr[%d]"
-                 , $time, cce_id_i, set_i, dir_ram_addr);
-      end
-      if (r_v_i) begin
-        $display("[%t] CCE[%d] read WG[%d]", $time, cce_id_i, set_i);
-      end
-    end
-  end
-  */
-
   always_ff @(posedge clk_i) begin
     if (reset_i) begin
       state_r <= RESET;

diff --git a/bp_me/src/v/cce/bp_cce_msg_cached.v b/bp_me/src/v/cce/bp_cce_msg_cached.v
@@ -198,16 +198,6 @@ module bp_cce_msg_cached
   wire fwd_mod_v_li = decoded_inst_i.spec_w_v;
   wire state_v_li = decoded_inst_i.spec_w_v;
 
-  /*
-  wire squash_v_li = (decoded_inst_i.spec_cmd == e_spec_cmd_squash)
-                     || (decoded_inst_i.spec_cmd == e_spec_cmd_clear);
-  wire fwd_mod_v_li = (decoded_inst_i.spec_cmd == e_spec_cmd_fwd_mod)
-                      || (decoded_inst_i.spec_cmd == e_spec_cmd_clear);
-  wire state_v_li = (decoded_inst_i.spec_cmd == e_spec_cmd_fwd_mod)
-                    || (decoded_inst_i.spec_cmd == e_spec_cmd_clear);
-  */
-
-  // TODO: way group calculation needs to change for npot
   bp_cce_spec
     #(.num_way_groups_p(num_way_groups_lp))
     spec_bits
@@ -356,10 +346,6 @@ module bp_cce_msg_cached
       // Speculative access response
       // Note: speculative access is only supported for cached requests
       if (mem_resp_li.payload.speculative) begin
-        // TODO: remove assertion
-        // synopsys translate_off
-        assert(spec_bits_v_lo) else $error("speculative memory response but spec_bits invalid output");
-        // synopsys translate_on
 
         if (spec_bits_lo.spec) begin // speculation not resolved yet
           // do nothing, wait for speculation to be resolved
@@ -748,7 +734,6 @@ module bp_cce_msg_cached
             mem_resp_yumi_o = decoded_inst_i.mem_resp_yumi;
             // decrement the fence counter when dequeueing the memory response
             fence_dec = mem_resp_v_i & mem_resp_yumi_o;
-            // TODO: dec pending bit?
             // clear pending bit
             pending_w_v_o = 1'b1;
             pending_w_addr_lo = mem_resp_li.addr;