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Inspektor Gadget is a set of tools and framework for data collection and system inspection on Kubernetes clusters and Linux hosts using eBPF
Some reference and example networking plugins, maintained by the CNI team.
contaiNERD CTL - Docker-compatible CLI for containerd, with support for Compose, Rootless, eStargz, OCIcrypt, IPFS, ...
User documentation for Knative components.
Python toolkit for quantitative finance
A curated list of insanely awesome libraries, packages and resources for Quants (Quantitative Finance)
High-performance TensorFlow library for quantitative finance.
DiceDB is an open source, redis-compliant, reactive, scalable, highly-available, unified cache optimized for modern hardware.
Useful scripts, udfs, views, and other utilities for migration and data warehouse operations in BigQuery.
Labs and demos for courses for GCP Training (http://cloud.google.com/training).
Guestbook is an example application showing basic usage of Google App Engine
Microservice creation and Machine Learning Model Deployment using FastAPI
Public repo for DeepLearning.AI MLEP Specialization
miniSpartan6+ (Spartan6) FPGA based MP3 Player
A deep learning method for event driven stock market prediction. Deep learning is useful for event-driven stock price movement prediction by proposing a novel neural tensor network for learning eve…
BTP Project : Network Traffic Prediction || A probabilistic deep machinery that models the traffic characteristics of hosts on a network and effectively forecasts the network traffic patterns, such…
Solution to COA LAB Assgn, IIT Kharagpur
A blog for LLVM(v9.0.0 or v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM and accomplish a complete project for FPGA High-Level Synthesis with it.
AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first …
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip …
Image Processing Toolbox in Verilog using Basys3 FPGA
5-stage pipelined 32-bit MIPS microprocessor in Verilog
Redis Operator creates/configures/manages high availability redis with sentinel automatic failover atop Kubernetes.
Kubernetes Universal Declarative Operator (KUDO)