Skip to content

Commit

Permalink
Clean up RELEASE_DELAY_G generic
Browse files Browse the repository at this point in the history 
In most instances it was unnecessary or improperly named
  • Loading branch information
@bengineerd
bengineerd committed Feb 27, 2020
1 parent b14cc9f commit 14ed437
Show file tree
Hide file tree
Showing 8 changed files with 219 additions and 231 deletions.
1 change: 0 additions & 1 deletion axi/axi-lite/rtl/AxiLiteRamSyncStatusVector.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,6 @@ entity AxiLiteRamSyncStatusVector is
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false; -- true if reset is asynchronous, false if reset is synchronous
COMMON_CLK_G : boolean := false; -- True if wrClk and rdClk are the same clock
RELEASE_DELAY_G : positive := 3; -- Delay between deassertion of async and sync resets
IN_POLARITY_G : slv := "1"; -- 0 for active LOW, 1 for active HIGH (for statusIn port)
OUT_POLARITY_G : sl := '1'; -- 0 for active LOW, 1 for active HIGH (for irqOut port)
SYNTH_CNT_G : slv := "1"; -- Set to 1 for synthesising counter RTL, '0' to not synthesis the counter
Expand Down
76 changes: 37 additions & 39 deletions base/sync/rtl/SyncStatusVector.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,27 +23,27 @@ use surf.StdRtlPkg.all;

entity SyncStatusVector is
generic (
TPD_G : time := 1 ns; -- Simulation FF output delay
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false;-- true if reset is asynchronous, false if reset is synchronous
COMMON_CLK_G : boolean := false;-- True if wrClk and rdClk are the same clock
RELEASE_DELAY_G : positive := 3; -- Delay between deassertion of async and sync resets
IN_POLARITY_G : slv := "1"; -- 0 for active LOW, 1 for active HIGH (for statusIn port)
OUT_POLARITY_G : sl := '1'; -- 0 for active LOW, 1 for active HIGH (for irqOut port)
USE_DSP_G : string := "no"; -- "no" for no DSP implementation, "yes" to use DSP slices
SYNTH_CNT_G : slv := "1"; -- Set to 1 for synthesising counter RTL, '0' to not synthesis the counter
CNT_RST_EDGE_G : boolean := true; -- true if counter reset should be edge detected, else level detected
CNT_WIDTH_G : positive := 32; -- Counters' width
WIDTH_G : positive := 16); -- Status vector width
TPD_G : time := 1 ns; -- Simulation FF output delay
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false; -- true if reset is asynchronous, false if reset is synchronous
COMMON_CLK_G : boolean := false; -- True if wrClk and rdClk are the same clock
SYNC_STAGES_G : positive := 3; -- Synchronization stages between statusIn and statusOut
IN_POLARITY_G : slv := "1"; -- 0 for active LOW, 1 for active HIGH (for statusIn port)
OUT_POLARITY_G : sl := '1'; -- 0 for active LOW, 1 for active HIGH (for irqOut port)
USE_DSP_G : string := "no"; -- "no" for no DSP implementation, "yes" to use DSP slices
SYNTH_CNT_G : slv := "1"; -- Set to 1 for synthesising counter RTL, '0' to not synthesis the counter
CNT_RST_EDGE_G : boolean := true; -- true if counter reset should be edge detected, else level detected
CNT_WIDTH_G : positive := 32; -- Counters' width
WIDTH_G : positive := 16); -- Status vector width
port (
---------------------------------------------
-- Input Status bit Signals (wrClk domain)
---------------------------------------------
statusIn : in slv(WIDTH_G-1 downto 0);-- Data to be 'synced'
statusIn : in slv(WIDTH_G-1 downto 0); -- Data to be 'synced'
---------------------------------------------
-- Output Status bit Signals (rdClk domain)
---------------------------------------------
statusOut : out slv(WIDTH_G-1 downto 0);-- Synced data
statusOut : out slv(WIDTH_G-1 downto 0); -- Synced data
---------------------------------------------
-- Status Bit Counters Signals (rdClk domain)
---------------------------------------------
Expand Down Expand Up @@ -87,9 +87,9 @@ entity SyncStatusVector is
-- Clocks and Reset Ports
---------------------------------------------
wrClk : in sl;
wrRst : in sl := '0';
wrRst : in sl := '0';
rdClk : in sl;
rdRst : in sl := '0');
rdRst : in sl := '0');
end SyncStatusVector;

architecture rtl of SyncStatusVector is
Expand All @@ -98,7 +98,7 @@ architecture rtl of SyncStatusVector is
irqOut : sl;
hitVector : slv(WIDTH_G-1 downto 0);
end record RegType;

constant REG_INIT_C : RegType := (
not(OUT_POLARITY_G),
(others => '0'));
Expand All @@ -107,14 +107,14 @@ architecture rtl of SyncStatusVector is
signal rin : RegType;

signal statusStrobe : slv(WIDTH_G-1 downto 0);

begin

SyncVec_Inst : entity surf.SynchronizerVector
generic map (
TPD_G => TPD_G,
BYPASS_SYNC_G => COMMON_CLK_G,
STAGES_G => RELEASE_DELAY_G,
STAGES_G => SYNC_STAGES_G,
WIDTH_G => WIDTH_G)
port map (
clk => rdClk,
Expand All @@ -123,31 +123,29 @@ begin

SyncOneShotCntVec_Inst : entity surf.SynchronizerOneShotCntVector
generic map (
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => RST_ASYNC_G,
COMMON_CLK_G => COMMON_CLK_G,
RELEASE_DELAY_G => RELEASE_DELAY_G,
IN_POLARITY_G => IN_POLARITY_G,
OUT_POLARITY_G => "1",
USE_DSP_G => USE_DSP_G,
SYNTH_CNT_G => SYNTH_CNT_G,
CNT_RST_EDGE_G => CNT_RST_EDGE_G,
CNT_WIDTH_G => CNT_WIDTH_G,
WIDTH_G => WIDTH_G)
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => RST_ASYNC_G,
COMMON_CLK_G => COMMON_CLK_G,
IN_POLARITY_G => IN_POLARITY_G,
OUT_POLARITY_G => "1",
USE_DSP_G => USE_DSP_G,
SYNTH_CNT_G => SYNTH_CNT_G,
CNT_RST_EDGE_G => CNT_RST_EDGE_G,
CNT_WIDTH_G => CNT_WIDTH_G,
WIDTH_G => WIDTH_G)
port map (
-- Write Ports (wrClk domain)
-- Write Ports (wrClk domain)
wrClk => wrClk,
wrRst => wrRst,
dataIn => statusIn,
-- Read Ports (rdClk domain)
rdClk => rdClk,
rdRst => rdRst,
rollOverEn => rollOverEnIn,
cntRst => cntRstIn,
dataOut => statusStrobe,
cntOut => cntOut,
-- Clocks and Reset Ports
wrClk => wrClk,
wrRst => wrRst,
rdClk => rdClk,
rdRst => rdRst);
cntOut => cntOut);

comb : process (irqEnIn, r, rdRst, statusStrobe) is
variable i : integer;
Expand Down Expand Up @@ -178,7 +176,7 @@ begin

-- Outputs
irqOut <= r.irqOut;

end process comb;

seq : process (rdClk, rdRst) is
Expand Down
8 changes: 2 additions & 6 deletions base/sync/rtl/SynchronizerOneShotCnt.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,6 @@ entity SynchronizerOneShotCnt is
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false; -- true if reset is asynchronous, false if reset is synchronous
COMMON_CLK_G : boolean := false; -- True if wrClk and rdClk are the same clock
RELEASE_DELAY_G : positive := 3; -- Delay between deassertion of async and sync resets
IN_POLARITY_G : sl := '1'; -- 0 for active LOW, 1 for active HIGH (dataIn port)
OUT_POLARITY_G : sl := '1'; -- 0 for active LOW, 1 for active HIGH (dataOut port)
USE_DSP_G : string := "no"; -- "no" for no DSP implementation, "yes" to use DSP slices
Expand Down Expand Up @@ -116,8 +115,7 @@ begin
RST_POLARITY_G => RST_POLARITY_G,
OUT_POLARITY_G => '1',
RST_ASYNC_G => RST_ASYNC_G,
BYPASS_SYNC_G => COMMON_CLK_G,
STAGES_G => (RELEASE_DELAY_G-1))
BYPASS_SYNC_G => COMMON_CLK_G)
port map (
clk => wrClk,
rst => wrRst,
Expand All @@ -132,8 +130,7 @@ begin
RST_POLARITY_G => RST_POLARITY_G,
OUT_POLARITY_G => '1',
RST_ASYNC_G => RST_ASYNC_G,
BYPASS_SYNC_G => COMMON_CLK_G,
STAGES_G => (RELEASE_DELAY_G-1))
BYPASS_SYNC_G => COMMON_CLK_G)
port map (
clk => wrClk,
rst => wrRst,
Expand Down Expand Up @@ -214,7 +211,6 @@ begin
generic map (
TPD_G => TPD_G,
COMMON_CLK_G => COMMON_CLK_G,
SYNC_STAGES_G => RELEASE_DELAY_G,
DATA_WIDTH_G => CNT_WIDTH_G)
port map (
-- Asynchronous Reset
Expand Down
99 changes: 47 additions & 52 deletions base/sync/rtl/SynchronizerOneShotCntVector.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,18 +22,17 @@ use surf.StdRtlPkg.all;

entity SynchronizerOneShotCntVector is
generic (
TPD_G : time := 1 ns; -- Simulation FF output delay
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false; -- true if reset is asynchronous, false if reset is synchronous
COMMON_CLK_G : boolean := false; -- True if wrClk and rdClk are the same clock
RELEASE_DELAY_G : positive := 3; -- Delay between deassertion of async and sync resets
IN_POLARITY_G : slv := "1"; -- 0 for active LOW, 1 for active HIGH (dataIn port)
OUT_POLARITY_G : slv := "1"; -- 0 for active LOW, 1 for active HIGH (dataOut port)
USE_DSP_G : string := "no"; -- "no" for no DSP implementation, "yes" to use DSP slices
SYNTH_CNT_G : slv := "1"; -- Set to 1 for synthesising counter RTL, '0' to not synthesis the counter
CNT_RST_EDGE_G : boolean := true; -- true if counter reset should be edge detected, else level detected
CNT_WIDTH_G : positive := 16;
WIDTH_G : positive := 16);
TPD_G : time := 1 ns; -- Simulation FF output delay
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false; -- true if reset is asynchronous, false if reset is synchronous
COMMON_CLK_G : boolean := false; -- True if wrClk and rdClk are the same clock
IN_POLARITY_G : slv := "1"; -- 0 for active LOW, 1 for active HIGH (dataIn port)
OUT_POLARITY_G : slv := "1"; -- 0 for active LOW, 1 for active HIGH (dataOut port)
USE_DSP_G : string := "no"; -- "no" for no DSP implementation, "yes" to use DSP slices
SYNTH_CNT_G : slv := "1"; -- Set to 1 for synthesising counter RTL, '0' to not synthesis the counter
CNT_RST_EDGE_G : boolean := true; -- true if counter reset should be edge detected, else level detected
CNT_WIDTH_G : positive := 16;
WIDTH_G : positive := 16);
port (

-- Write Ports (wrClk domain)
Expand Down Expand Up @@ -94,16 +93,15 @@ architecture rtl of SynchronizerOneShotCntVector is
begin

CNT_RST_EDGE : if (CNT_RST_EDGE_G = true) generate

SyncOneShot_1 : entity surf.SynchronizerOneShot
generic map (
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => RST_ASYNC_G,
BYPASS_SYNC_G => COMMON_CLK_G,
OUT_DELAY_G => RELEASE_DELAY_G,
IN_POLARITY_G => RST_POLARITY_G,
OUT_POLARITY_G => RST_POLARITY_G)
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => RST_ASYNC_G,
BYPASS_SYNC_G => COMMON_CLK_G,
IN_POLARITY_G => RST_POLARITY_G,
OUT_POLARITY_G => RST_POLARITY_G)
port map (
clk => wrClk,
rst => wrRst,
Expand All @@ -113,20 +111,19 @@ begin
end generate;

CNT_RST_LEVEL : if (CNT_RST_EDGE_G = false) generate

Synchronizer_0 : entity surf.Synchronizer
generic map (
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
OUT_POLARITY_G => '1',
RST_ASYNC_G => RST_ASYNC_G,
BYPASS_SYNC_G => COMMON_CLK_G,
STAGES_G => (RELEASE_DELAY_G-1))
BYPASS_SYNC_G => COMMON_CLK_G)
port map (
clk => wrClk,
rst => wrRst,
dataIn => cntRst,
dataOut => cntRstSync);
dataOut => cntRstSync);

end generate;

Expand All @@ -140,22 +137,21 @@ begin
RST_POLARITY_G => RST_POLARITY_G,
OUT_POLARITY_G => '1',
RST_ASYNC_G => RST_ASYNC_G,
BYPASS_SYNC_G => COMMON_CLK_G,
STAGES_G => (RELEASE_DELAY_G-1))
BYPASS_SYNC_G => COMMON_CLK_G)
port map (
clk => wrClk,
rst => wrRst,
dataIn => rollOverEn(i),
dataOut => rollOverEnSync(i));
dataOut => rollOverEnSync(i));

U_SyncOneShot : entity surf.SynchronizerOneShot
generic map (
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => RST_ASYNC_G,
BYPASS_SYNC_G => COMMON_CLK_G,
IN_POLARITY_G => IN_POLARITY_C(i),
OUT_POLARITY_G => OUT_POLARITY_C(i))
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => RST_ASYNC_G,
BYPASS_SYNC_G => COMMON_CLK_G,
IN_POLARITY_G => IN_POLARITY_C(i),
OUT_POLARITY_G => OUT_POLARITY_C(i))
port map (
clk => rdClk,
rst => rdRst,
Expand All @@ -164,30 +160,29 @@ begin

SyncOneShotCnt_Inst : entity surf.SynchronizerOneShotCnt
generic map (
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => RST_ASYNC_G,
COMMON_CLK_G => true, -- status counter bus synchronization done outside
RELEASE_DELAY_G => RELEASE_DELAY_G,
IN_POLARITY_G => IN_POLARITY_C(i),
OUT_POLARITY_G => OUT_POLARITY_C(i),
USE_DSP_G => USE_DSP_G,
SYNTH_CNT_G => SYNTH_CNT_C(i),
CNT_RST_EDGE_G => CNT_RST_EDGE_G,
CNT_WIDTH_G => CNT_WIDTH_G)
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => RST_ASYNC_G,
COMMON_CLK_G => true, -- status counter bus synchronization done outside
IN_POLARITY_G => IN_POLARITY_C(i),
OUT_POLARITY_G => OUT_POLARITY_C(i),
USE_DSP_G => USE_DSP_G,
SYNTH_CNT_G => SYNTH_CNT_C(i),
CNT_RST_EDGE_G => CNT_RST_EDGE_G,
CNT_WIDTH_G => CNT_WIDTH_G)
port map (
-- Write Ports (wrClk domain)
-- Write Ports (wrClk domain)
wrClk => wrClk,
wrRst => wrRst,
dataIn => dataIn(i),
-- Read Ports (rdClk domain)
-- Read Ports (rdClk domain)
rdClk => wrClk, -- status counter bus synchronization done outside
rdRst => wrRst,
rollOverEn => rollOverEnSync(i),
cntRst => cntRstSync,
dataOut => open,
cntOut => cntWrDomain(i),
-- Clocks and Reset Ports
wrClk => wrClk,
wrRst => wrRst,
rdClk => wrClk, -- status counter bus synchronization done outside
rdRst => wrRst);
cntOut => cntWrDomain(i));


GEN_MAP :
for j in (CNT_WIDTH_G-1) downto 0 generate
Expand Down
Loading

0 comments on commit 14ed437

Please sign in to comment.