updated SRAM settings

Alefal44 · Nov 4, 2021 · bdf341d · bdf341d
1 parent aea2035
commit bdf341d
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Showing 4 changed files with 38 additions and 16 deletions.
diff --git a/ACDC/ACDC.ioc b/ACDC/ACDC.ioc
@@ -107,6 +107,21 @@ Dma.SPI3_TX.2.SyncEnable=DISABLE
 Dma.SPI3_TX.2.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
 Dma.SPI3_TX.2.SyncRequestNumber=1
 Dma.SPI3_TX.2.SyncSignalID=NONE
+FMC.CASLatency1=FMC_SDRAM_CAS_LATENCY_3
+FMC.ColumnBitsNumber1=FMC_SDRAM_COLUMN_BITS_NUM_9
+FMC.ExitSelfRefreshDelay1=7
+FMC.IPParameters=ColumnBitsNumber1,CASLatency1,SDClockPeriod1,SDClockPeriod2,ReadBurst1,ReadBurst2,LoadToActiveDelay1,ExitSelfRefreshDelay1,SelfRefreshTime1,RowCycleDelay1,RowCycleDelay2,WriteRecoveryTime1,RPDelay1,RPDelay2
+FMC.LoadToActiveDelay1=2
+FMC.RPDelay1=1
+FMC.RPDelay2=1
+FMC.ReadBurst1=FMC_SDRAM_RBURST_ENABLE
+FMC.ReadBurst2=FMC_SDRAM_RBURST_ENABLE
+FMC.RowCycleDelay1=8
+FMC.RowCycleDelay2=8
+FMC.SDClockPeriod1=FMC_SDRAM_CLOCK_PERIOD_2
+FMC.SDClockPeriod2=FMC_SDRAM_CLOCK_PERIOD_2
+FMC.SelfRefreshTime1=4
+FMC.WriteRecoveryTime1=3
 FREERTOS.FootprintOK=true
 FREERTOS.INCLUDE_vTaskDelayUntil=1
 FREERTOS.IPParameters=Tasks01,configUSE_PREEMPTION,configUSE_IDLE_HOOK,configUSE_TICK_HOOK,configUSE_MALLOC_FAILED_HOOK,INCLUDE_vTaskDelayUntil,configUSE_MUTEXES,configCHECK_FOR_STACK_OVERFLOW,FootprintOK

diff --git a/ACDC/Core/Inc/hardware.h b/ACDC/Core/Inc/hardware.h
@@ -8,11 +8,13 @@
 /* #define NO_CCM_RAM */
 #define DMA_RAM                      __attribute__ ((section (".dmadata")))
 #define USE_PLUS_RAM
-/* #define USE_ICACHE */
-/* #define USE_DCACHE */
+
+#ifdef NDEBUG
+#define USE_ICACHE
+#define USE_DCACHE
+#endif
 
 #define ARM_CYCLES_PER_SAMPLE       (480000000/AUDIO_SAMPLINGRATE) /* 480MHz / 48kHz */
-#define MAIN_LOOP_SLEEP_MS          20
 
 // todo: quad SPI
 /* #define USE_SPI_FLASH */
@@ -35,7 +37,7 @@
 
 #define USE_USBD_AUDIO
 #define USE_USBD_AUDIO_TX           // microphone
-/* #define USE_USBD_AUDIO_RX           // speaker */
+#define USE_USBD_AUDIO_RX           // speaker
 #define USE_USBD_FS
 #define USBD_HANDLE                 hUsbDeviceFS
 /* #define USBD_MAX_POWER              100 // 200mA for iPad compatibility */

diff --git a/ACDC/Core/Src/ACDC.cpp b/ACDC/Core/Src/ACDC.cpp
@@ -19,6 +19,11 @@
 #define XIBECA_PIN13 GPIOA, GPIO_PIN_7
 #define XIBECA_PIN14 GPIOA, GPIO_PIN_3
 
+#define XIBECA_PIN17 GPIOG, GPIO_PIN_12
+#define XIBECA_PIN18 GPIOG, GPIO_PIN_11
+#define XIBECA_PIN19 GPIOA, GPIO_PIN_15
+#define XIBECA_PIN20 GPIOA, GPIO_PIN_1
+
 #define XIBECA_PIN21 GPIOC, GPIO_PIN_6
 #define XIBECA_PIN22 GPIOC, GPIO_PIN_7
 #define XIBECA_PIN23 GPIOD, GPIO_PIN_12
@@ -103,7 +108,7 @@ void setup(){
   led_out2.outputMode();
   led_out3.outputMode();
   led_out4.outputMode();
-  // 
+
   for(size_t i=1; i<=12; ++i)
     setLed(i, NO_COLOUR);
 

diff --git a/ACDC/Core/Src/main.c b/ACDC/Core/Src/main.c
@@ -940,23 +940,23 @@ static void MX_FMC_Init(void)
   hsdram1.Instance = FMC_SDRAM_DEVICE;
   /* hsdram1.Init */
   hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
-  hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
+  hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9; // 8;
   hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_13;
   hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32;
   hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
-  hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_1;
+  hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3; // 1;
   hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
-  hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_DISABLE;
-  hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
+  hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2; // DISABLE;
+  hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE; // DISABLE;
   hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
   /* SdramTiming */
-  SdramTiming.LoadToActiveDelay = 16;
-  SdramTiming.ExitSelfRefreshDelay = 16;
-  SdramTiming.SelfRefreshTime = 16;
-  SdramTiming.RowCycleDelay = 16;
-  SdramTiming.WriteRecoveryTime = 16;
-  SdramTiming.RPDelay = 16;
-  SdramTiming.RCDDelay = 16;
+  SdramTiming.LoadToActiveDelay = 2; // 16;
+  SdramTiming.ExitSelfRefreshDelay = 7; // 16;
+  SdramTiming.SelfRefreshTime = 4; // 16;
+  SdramTiming.RowCycleDelay = 8; // 16;
+  SdramTiming.WriteRecoveryTime = 3; // 16;
+  SdramTiming.RPDelay = 1; // 0 causes assertion error; // 16;
+  SdramTiming.RCDDelay = 10; // 16;
 
   if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
   {