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core: add missing mandatory machine information CSRs and add basic as…
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…m tests for them
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@AleksandarLilic
AleksandarLilic committed Dec 22, 2024
1 parent 1a8e96f commit 5f91ebf
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Showing 5 changed files with 151 additions and 44 deletions.
21 changes: 16 additions & 5 deletions src/core.h
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Expand Up @@ -349,17 +349,28 @@ class core{
#endif

std::map<uint16_t, CSR> csr;
static constexpr std::array<CSR_entry, 14> supported_csrs = {{
static constexpr std::array<CSR_entry, 17> supported_csrs = {{
{CSR_TOHOST, "tohost", csr_perm_t::rw, 0u},

// Machine Information Registers
{CSR_MVENDORID, "mvendorid", csr_perm_t::warl_unimp, 0u},
{CSR_MARCHID, "marchid", csr_perm_t::warl_unimp, 0u},
{CSR_MIMPID, "mimpid", csr_perm_t::warl_unimp, 0u},
{CSR_MHARTID, "mhartid", csr_perm_t::ro, 0u},

// Machine Trap Setup
{CSR_MISA, "misa", csr_perm_t::warl_unimp, 0u},

// Machine Trap Handling
{CSR_MSCRATCH, "mscratch", csr_perm_t::rw, 0u},

// Machine Counter/Timers
{CSR_MCYCLE, "mcycle", csr_perm_t::rw, 0u},
{CSR_MINSTRET, "minstret", csr_perm_t::rw, 0u},
{CSR_MCYCLEH, "mcycleh", csr_perm_t::rw, 0u},
{CSR_MINSTRETH, "minstreth", csr_perm_t::rw, 0u},
// read only CSRs
{CSR_MISA, "misa", csr_perm_t::warl_unimp, 0u},
{CSR_MHARTID, "mhartid", csr_perm_t::ro, 0u},
// read only user CSRs

// Unprivileged Counter/Timers
{CSR_CYCLE, "cycle", csr_perm_t::ro, 0u},
{CSR_TIME, "time", csr_perm_t::ro, 0u},
{CSR_INSTRET, "instret", csr_perm_t::ro, 0u},
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50 changes: 33 additions & 17 deletions src/defines.h
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Expand Up @@ -110,23 +110,39 @@
#define INST_HINT_LOG_START 0x01002013 // slti x0, x0, 0x10
#define INST_HINT_LOG_END 0x01102013 // slti x0, x0, 0x11

// CSR addresses
#define CSR_TOHOST 0x51e
#define CSR_MSCRATCH 0x340
#define CSR_MCYCLE 0xb00
#define CSR_MINSTRET 0xb02
#define CSR_MCYCLEH 0xb80
#define CSR_MINSTRETH 0xb82
// read-only CSRs
#define CSR_MISA 0x301
#define CSR_MHARTID 0xf14
// read only user CSRs
#define CSR_CYCLE 0xC00
#define CSR_TIME 0xC01
#define CSR_INSTRET 0xC02
#define CSR_CYCLEH 0xC80
#define CSR_TIMEH 0xC81
#define CSR_INSTRETH 0xC82
#define CSR_TOHOST 0x51E

// Machine-level CSR addresses
// Machine Information Registers
#define CSR_MVENDORID 0xF11 // MRO
#define CSR_MARCHID 0xF12 // MRO
#define CSR_MIMPID 0xF13 // MRO
#define CSR_MHARTID 0xF14 // MRO
// Machine Trap Setup
//#define CSR_MSTATUS 0x300 // MRW
#define CSR_MISA 0x301 // MRW
//#define CSR_MIE 0x304 // MRW
//#define CSR_MTVEC 0x305 // MRW
// Machine Trap Handling
#define CSR_MSCRATCH 0x340 // MRW
//#define CSR_MEPC 0x341 // MRW
//#define CSR_MCAUSE 0x342 // MRW
//#define CSR_MTVAL 0x343 // MRW
//#define CSR_MIP 0x344 // MRW
// Machine Counter/Timers
#define CSR_MCYCLE 0XB00 // MRW
#define CSR_MINSTRET 0XB02 // MRW
#define CSR_MCYCLEH 0XB80 // MRW
#define CSR_MINSTRETH 0XB82 // MRW

// Unprivileged CSR addresses
// Unprivileged Counter/Timers
#define CSR_CYCLE 0xC00 // URO
#define CSR_TIME 0xC01 // URO
#define CSR_INSTRET 0xC02 // URO
#define CSR_CYCLEH 0xC80 // URO
#define CSR_TIMEH 0xC81 // URO
#define CSR_INSTRETH 0xC82 // URO

// Macros
#define CASE_DECODER(op) \
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7 changes: 4 additions & 3 deletions src/types.h
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Expand Up @@ -139,9 +139,10 @@ enum class scp_custom_op_t {
};

enum class csr_perm_t {
ro = 0b00,
rw = 0b01,
warl_unimp = 0b10
ro = 0b00, // read-only
rw = 0b01, // read-write
warl = 0b10, // write-any-read-legal
warl_unimp = 0b11, // warl unimplemented -> always returns 0
};

enum class rf_names_t { mode_x, mode_abi };
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68 changes: 65 additions & 3 deletions sw/baremetal/asm_rv32i_zicsr/main.S
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Expand Up @@ -52,6 +52,47 @@ csr_rs_x0:
csrrs x6, 0x340, x0
bne x6, x7, fail # x7 value should still be in 0x340 on x0 'writes' to CSR

mvendorid_read:
csrr x26, CSR_MVENDORID
TEST_INC
bne x26, x0, fail # mvendorid is 0 when not implemented

mvendor_write:
li x26, 0x80000000
csrw CSR_MVENDORID, x26
TEST_INC
csrr x26, CSR_MVENDORID
bne x26, x0, fail # still 0 when writing to unimplemented mvendorid

marchid_read:
csrr x26, CSR_MARCHID
TEST_INC
bne x26, x0, fail # marchid is 0 when not implemented

marchid_write:
li x26, 0x80000000
csrw CSR_MARCHID, x26
TEST_INC
csrr x26, CSR_MARCHID
bne x26, x0, fail # still 0 when writing to unimplemented marchid

mimpid_read:
csrr x26, CSR_MIMPID
TEST_INC
bne x26, x0, fail # mimpid is 0 when not implemented

mimpid_write:
li x26, 0x80000000
csrw CSR_MIMPID, x26
TEST_INC
csrr x26, CSR_MIMPID
bne x26, x0, fail # still 0 when writing to unimplemented mimpid

mhartid_read:
csrr x26, CSR_MHARTID
TEST_INC
bne x26, x0, fail # mhartid is 0, only one hart

misa_read:
csrr x26, CSR_MISA
TEST_INC
Expand All @@ -64,10 +105,31 @@ misa_write:
csrr x26, CSR_MISA
bne x26, x0, fail # still 0 when writing to unimplemented misa

mhartid_read:
csrr x26, CSR_MHARTID
mcycle_read:
csrr x26, CSR_MCYCLE
TEST_INC
bne x26, x0, fail # mhartid is 0, only one hart
beq x26, x0, fail # mcycle shouldn't be 0 at this point

mcycle_write:
li x26, 0x0
csrw CSR_MCYCLE, x26
TEST_INC
csrr x26, CSR_MCYCLE
li x27, 0x20
bge x26, x27, fail # mcycle should be greater than 0 but less than 32 clk

minstret_read:
csrr x26, CSR_MINSTRET
TEST_INC
beq x26, x0, fail # minstret shouldn't be 0 at this point

minstret_write:
li x26, 0x0
csrw CSR_MINSTRET, x26
TEST_INC
csrr x26, CSR_MINSTRET
li x27, 0x20
bge x26, x27, fail # minstret should be greater than 0 but less than 32 inst

j pass

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49 changes: 33 additions & 16 deletions sw/baremetal/common/csr.h
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@@ -1,21 +1,38 @@
#ifndef CSR_H
#define CSR_H

#define CSR_TOHOST 0x51e
#define CSR_MSCRATCH 0x340
#define CSR_MCYCLE 0xb00
#define CSR_MINSTRET 0xb02
#define CSR_MCYCLEH 0xb80
#define CSR_MINSTRETH 0xb82
// read-only CSRs
#define CSR_MISA 0x301
#define CSR_MHARTID 0xf14
// read only user CSRs
#define CSR_CYCLE 0xC00
#define CSR_TIME 0xC01
#define CSR_INSTRET 0xC02
#define CSR_CYCLEH 0xC80
#define CSR_TIMEH 0xC81
#define CSR_INSTRETH 0xC82
#define CSR_TOHOST 0x51E

// Machine-level CSR addresses
// Machine Information Registers
#define CSR_MVENDORID 0xF11 // MRO
#define CSR_MARCHID 0xF12 // MRO
#define CSR_MIMPID 0xF13 // MRO
#define CSR_MHARTID 0xF14 // MRO
// Machine Trap Setup
//#define CSR_MSTATUS 0x300 // MRW
#define CSR_MISA 0x301 // MRW
//#define CSR_MIE 0x304 // MRW
//#define CSR_MTVEC 0x305 // MRW
// Machine Trap Handling
#define CSR_MSCRATCH 0x340 // MRW
//#define CSR_MEPC 0x341 // MRW
//#define CSR_MCAUSE 0x342 // MRW
//#define CSR_MTVAL 0x343 // MRW
//#define CSR_MIP 0x344 // MRW
// Machine Counter/Timers
#define CSR_MCYCLE 0XB00 // MRW
#define CSR_MINSTRET 0XB02 // MRW
#define CSR_MCYCLEH 0XB80 // MRW
#define CSR_MINSTRETH 0XB82 // MRW

// Unprivileged CSR addresses
// Unprivileged Counter/Timers
#define CSR_CYCLE 0xC00 // URO
#define CSR_TIME 0xC01 // URO
#define CSR_INSTRET 0xC02 // URO
#define CSR_CYCLEH 0xC80 // URO
#define CSR_TIMEH 0xC81 // URO
#define CSR_INSTRETH 0xC82 // URO

#endif

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