Altera Advanced Synthesis Cookbook 11.0

Exploring Wave Pipeline Designs in FPGAs

Control and status register code generator toolchain

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

折腾交换机

Send video/audio over HDMI on an FPGA

An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components

System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers

SystemRDL 2.0 language compiler front-end

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

Announcements related to Verilator

SystemVerilog linter