Ali-Moayed / ARM_CPU Public

Notifications You must be signed in to change notification settings
Fork 2
Star 4

implementation of ARM with Verilog

4 stars 2 forks Branches Tags Activity

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 23 Commits
.gitattributes		.gitattributes
AluControl.v		AluControl.v
CPU-Test.v		CPU-Test.v
CPU-Test_Piped.v		CPU-Test_Piped.v
DataMemory.v		DataMemory.v
Multiplexer.v		Multiplexer.v
PReg.v		PReg.v
README.md		README.md
ShiftL2.v		ShiftL2.v
adder.v		adder.v
alu.v		alu.v
clk.v		clk.v
controll_unit.v		controll_unit.v
instrn mem.v		instrn mem.v
pc.v		pc.v
registerBank.v		registerBank.v
signextended.v		signextended.v
test.v		test.v
test_bench.v		test_bench.v

Repository files navigation

ARM_CPU

implementation of ARM cpu with Verilog (CPU-Test)

Includes:

ALU
RegisterBank
Clock
Adder
ProgramCounter
ControlUnit
AluControl
ShiftLeft2
DataMemory
InstructionMemory
SignExtended
Multiplexer

About

implementation of ARM with Verilog

Report repository

Releases

No releases published

Packages

No packages published

Contributors 3

Languages

Verilog 100.0%