fixed w ide help

hw3/gus-tb.sv

@@ -6,23 +6,23 @@ module top ();
 	logic [3:0] y;
 
 //positional assign rather than name delcaration
-	top UUT (s,a,b,y);
+top UUT (s,a,b,y);
 	int _s = 0;
 	int _a = 0;
 	int _b = 0;
 //where does the assert go?
-	assert((y == a[3:0] + b[3:0]) & (s ==0))
-		else $error("FAIL: opcode is add(00), input is %b and %b, output is %b",a[3:0],b[3:0], y);
+	//assert((y == a[3:0] + b[3:0]) & (s ==0))
+		//else $error("FAIL: opcode is add(00), input is %b and %b, output is %b",a,b, y);
 	initial begin
 			for (int i = 0; i <= 3; i++) begin
 				_s ++;
 				for (int j = 0; j <= 15; j++) begin
-					_a++
+					_a++;
 						for (int k = 0; k <= 15; k++) begin
-							_b++
+							_b++;
 								//can I assign int to logic?
 								// this should be fine
-								#10 s = _s, a=_a, b=_b;
+								#10 s = _s; a=_a; b=_b;
 						end
 				end
 			end

hw3/top.sv

@@ -5,12 +5,10 @@ module top_module (
 	output [3:0] y
 	);
 
-always@(*) begin
+always@(*) 
 	case(s)
 		2'b00: y = a + b;
 		2'b01: y = a << b[1:0];
 		2'b10: y = a & b;
-		2'b11: y = 4'b0001;
-	endcase
+		2'b11: y = 4'b0001;		
 
-		end