-
Notifications
You must be signed in to change notification settings - Fork 1
/
Copy pathTLB_Cache.cpp
1633 lines (1486 loc) · 63.5 KB
/
TLB_Cache.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
#include "utils.h"
#include <boost/preprocessor.hpp>
#include "TLB.h"
#include "ID_Cache.h"
#define TLB_HIT 1
#define TLB_MISS 1
#define L1_HIT 2
#define L2_HIT 18
#define L3_HIT 12
#define page_fault_latency 1
#define chunk_allocation_plus_page_fault_latency 2
#define iqueue_size 64
uint64_t num_local[num_nodes]={0};
uint64_t num_remote[num_nodes]={0};
uint64_t num_remote_pages[num_nodes]={0};
int32_t num_page_swaps[num_nodes]={0};
uint64_t avg_page_access_time[num_nodes]={0};
uint64_t num_icache_misses[num_nodes][core_count]={0};
uint64_t num_icache_hits[num_nodes][core_count]={0};
uint64_t num_dcache_misses[num_nodes][core_count]={0};
uint64_t num_unique_dcache_misses[num_nodes][core_count]={0};
uint64_t num_dcache_hits[num_nodes][core_count]={0};
uint64_t num_l2_access[num_nodes][core_count]={0};
uint64_t num_l2_hits[num_nodes][core_count]={0};
uint64_t num_l3_access[num_nodes]={0};
uint64_t num_l3_hits[num_nodes]={0};
uint64_t num_l3_misses[num_nodes]={0};
uint64_t num_dl1_writebacks[num_nodes][core_count]={0};
uint64_t num_l2_writebacks[num_nodes][core_count]={0};
uint64_t num_l3_writebacks[num_nodes]={0};
// queue for per-core instruction stream on a node shared by Pintool
queue<INST> core_inst_stream[num_nodes][core_count];
struct RDMA_queue_entry
{
int pkt_count=0;// if packets have received has been transferred
uint64_t page_addr;
int start_cycle=0;
int complete_cycle=0;
};
map<uint64_t,RDMA_queue_entry>RDMA_request_queue[num_nodes];
#define mshr 8 // no. of enetries in mshr in each cache-level
// fetches sent to cache
struct INST_FETCH_QUEUE
{
INST ins;
// int ins_type;
int64_t request_cycle;
bool tlb_fetched;
int64_t tlb_complete_cycle;
bool mem_fetched;
int64_t mem_complete_cycle;
INST_FETCH_QUEUE()
{
tlb_fetched = false;
mem_fetched = false;
request_cycle = 0;
tlb_complete_cycle = 0;
mem_complete_cycle = 0;
}
bool operator<(const INST_FETCH_QUEUE &temp) const
{
return (ins.ins_id > temp.ins.ins_id);
}
};
struct merged_LLC_mshr
{
int core_id;
uint64_t ins_id;
char source_cache;
};
// this structure holds misses from tlb/cache in mshr
struct miss_queue
{
INST_FETCH_QUEUE inst_fetch;
uint64_t ins_id;
uint64_t ins_vaddr;
uint64_t paddr;
int node_id;
int thread_id;
int64_t request_cycle;
int64_t complete_cycle;
char source_cache; // request coming from I or D cache
int core_id;
bool write;
uint64_t mem_trans_id;
int cache_access_size;
uint64_t L1_cache_miss_complete_cycle;
uint64_t L2_cache_miss_complete_cycle;
uint64_t L3_cache_miss_complete_cycle;
uint64_t memory_start_cycle;
vector <uint64_t>ld_str_dest;
vector <merged_LLC_mshr>merged_mshr_in_shared_LLC;
miss_queue()
{
}
};
deque<miss_queue> temp[num_nodes][core_count]; // temp to store the some instruction belonging to same block if there is no space in ins queue
queue<miss_queue> load_store_buffer[num_nodes][core_count];
// void fill_load_buffer(int node_id)
// {
// miss_queue temp;
// int id = 0;
// uint64_t vaddr = 0x7fa507f75e98;
// for (int i = 0; i < 100000; i++)
// {
// temp.ins_id = id;
// temp.ins_vaddr = vaddr;
// temp.inst_fetch.ins.proc_id = 0;
// id++;
// uint64_t k = rand() % 100000;
// int j = rand() % 2;
// temp.write = j;
// if (j)
// {
// temp.cache_access_size = 1 + rand() % 5;
// }
// else
// {
// temp.cache_access_size = 1 + rand() % 5;
// }
// if (i % 2)
// {
// vaddr += k;
// }
// else
// vaddr -= k;
// temp.node_id = node_id;
// temp.core_id = (rand()) % core_count;
// load_store_buffer[node_id][temp.core_id].push(temp);
// }
// }
vector<miss_queue> itlb_miss_buffer[num_nodes][core_count];
vector<miss_queue> itlb_wait_buffer[num_nodes][core_count];
vector<miss_queue> il1_miss_buffer[num_nodes][core_count];
vector<miss_queue> dl1_miss_buffer[num_nodes][core_count];
vector<miss_queue> il1_wait_buffer[num_nodes][core_count];
vector<miss_queue> l2_miss_buffer[num_nodes][core_count];
vector<miss_queue> l3_miss_buffer[num_nodes];
vector<miss_queue> dtlb_miss_buffer[num_nodes][core_count];
map<uint64_t,pair<uint64_t,uint64_t>>page_fault_entry[num_nodes];
// for adding stalls due to branch misprediction
int branch_misprediction_penalty[num_nodes][core_count] = {0};
void update_LSQ_status(int, int, uint64_t);
INST_FETCH_QUEUE ITLB_HIT(INST &, int, int);
void ITLB_MISS(INST &, int, int);
void page_fault_entry_update(int);
void itlb_mshr_update(int, int);
void dtlb_search(int, int);
void DTLB_MISS(miss_queue &, int, int);
void dtlb_mshr_update(int, int);
bool dcache_hit(int, int, uint64_t, uint64_t, miss_queue &, int);
void dcache_miss(int, int, uint64_t, uint64_t, miss_queue);
void update_dcache_mshr(int, int);
void icache_search(int, int, uint64_t, uint64_t, INST_FETCH_QUEUE);
void update_icache_mshr(int, int);
void l2_cache_search(int, int, uint64_t, uint64_t, miss_queue, bool);
void update_l2_mshr(int, int);
void l3_cache_search(int, uint64_t, uint64_t, miss_queue, bool);
void update_l3_mshr(int);
void update_caches(int);
void get_ins_in_same_block(int, int, miss_queue);
void fetch_ins_in_same_block(int, int, INST_FETCH_QUEUE);
void send_to_memory(miss_queue, int,bool);
void perform_write_back(int, int, int, int16_t, uint64_t, CACHE_BASE::ACCESS_TYPE);
bool page_table_walk(pgd &, uint64_t, uint64_t &);
void handle_page_fault(pgd &, int, uint64_t, uint64_t &, local_addr_space &, bool &);
void memory_request_completed(int);
void LLC_to_memory(int);
void send_RDMA_read(uint64_t,int);
void broadcast_completed_LSQ(int, int, uint64_t);
// queue for fetched instructions
priority_queue<INST_FETCH_QUEUE> inst_queue[num_nodes][core_count];
// queue for storing (DTLB HIT OR MISS) AND DL1 HIT until it's complete cycle arrives.
queue<miss_queue> response_queue[num_nodes][core_count];
// used for giving a transaction-id to all the LLC cache misses
uint64_t mem_trans_id[num_nodes];// = {1,1};
// trans id is assigned separately and from reverse to distinguish it with cache line rem mem accesses
uint64_t RDMA_trans_id[num_nodes];
// used for sending the next instruction to iqueue, instructions are fetched out-of-order
// but are sent to ins_queue in-order
uint64_t last_ins_id[num_nodes][core_count] = {0};
void update_mshr(int node_id)
{
page_fault_entry_update(node_id);
memory_request_completed(node_id);
update_caches(node_id);
for (int i = 0; i < core_count; i++)
{
itlb_mshr_update(node_id, i);
dtlb_mshr_update(node_id, i);
}
LLC_to_memory(node_id);
update_l3_mshr(node_id);
for (int i = 0; i < core_count; i++)
{
update_l2_mshr(node_id, i);
update_icache_mshr(node_id, i);
update_dcache_mshr(node_id, i);
}
}
void itlb_search(int node_id, int core_id)
{
if (branch_misprediction_penalty[node_id][core_id] > 0)
{
return;
}
INST temp;
if (!core_inst_stream[node_id][core_id].empty())
{
temp = core_inst_stream[node_id][core_id].front();
}
else
return;
uint64_t vaddr = temp.addr;
// int core_id=temp.threadid%core_count;
int itlb_id = (node_id * core_count) + core_id;
uint64_t paddr = NULL;
// if(core_id==i)
// cout<<"good";
// else
// cout<<"bad";
bool itlb_hit = false;
itlb_hit = itlbs[itlb_id].AccessTLB(vaddr, TLB_BASE::ACCESS_TYPE_LOAD, temp.proc_id, paddr);
if (itlb_hit)
{
// handle branch instructions, add suitable penalty on mis-prediction
if (temp.is_Branch)
{
bool branch_prediction = predict_branch(temp.addr, node_id, core_id);
if (temp.branch_taken != branch_prediction)
{
// wrong branch prediction, penalty will be added during execution stage of this instruction
temp.branch_miss_predicted = 1;
}
else
{
// right branch prediction, but do not fetch in this cycle
temp.branch_miss_predicted = 0;
}
last_branch_result(temp.addr, temp.branch_taken, node_id, core_id);
}
// perform action for ITLB hit
INST_FETCH_QUEUE INST_temp = ITLB_HIT(temp, node_id, core_id);
uint64_t vaddr_offset = vaddr & 0xfff;
paddr = paddr << 12;
uint64_t cache_access_paddr = paddr + vaddr_offset;
// access_cache //read instructions of whole cache-line,
// don't access it for each instruction referring to same cacheline
// search in core icache
icache_search(node_id, core_id, cache_access_paddr, vaddr, INST_temp);
}
else
{
if (itlb_miss_buffer[node_id][core_id].size() < 1) // mshr for itlb is taken 1 (do not change, hard coded).
{
ITLB_MISS(temp, node_id, core_id);
}
}
}
INST_FETCH_QUEUE ITLB_HIT(INST &temp, int node_id, int coreid)
{
INST_FETCH_QUEUE INST_temp;
INST_temp.ins = temp;
INST_temp.tlb_fetched = true;
INST_temp.request_cycle = common_clock;
INST_temp.tlb_complete_cycle = INST_temp.request_cycle + TLB_HIT;
return INST_temp;
}
void ITLB_MISS(INST &temp, int node_id, int core_id)
{
miss_queue miss_temp;
miss_temp.ins_id = temp.ins_id;
miss_temp.inst_fetch.ins.proc_id = temp.proc_id;
miss_temp.ins_vaddr = temp.addr;
miss_temp.node_id = node_id;
miss_temp.thread_id = temp.threadid;
miss_temp.request_cycle = common_clock;
miss_temp.complete_cycle = -1;
uint64_t vaddr = temp.addr;
uint64_t paddr = NULL;
bool page_found_in_page_table = false;
uint64_t temp_vaddr = vaddr>>12;
if(page_fault_entry[node_id].find(temp_vaddr) != page_fault_entry[node_id].end())
{
pair<uint64_t,uint64_t> p = page_fault_entry[node_id][temp_vaddr];
miss_temp.paddr = p.first;
miss_temp.complete_cycle = p.second;
itlb_miss_buffer[node_id][core_id].push_back(miss_temp);
return;
}
page_found_in_page_table = page_table_walk(_pgd[node_id], vaddr, paddr);
if (page_found_in_page_table)
{
miss_temp.complete_cycle = miss_temp.request_cycle + TLB_MISS;
}
else
{
bool new_remote_chunk_allocated = false;
handle_page_fault(_pgd[node_id], node_id, vaddr, paddr, L[node_id], new_remote_chunk_allocated); // handle by allocating a new page in Local or Remote
if (new_remote_chunk_allocated == false)
miss_temp.complete_cycle = miss_temp.request_cycle + page_fault_latency; // page_fault complete after 'n' ms if free page (local/remote) is there
else
{
// if we are allocating remote page and remote memory is not available,
miss_temp.complete_cycle = miss_temp.request_cycle + chunk_allocation_plus_page_fault_latency; // add extra 'x' ms to allocate a remote memory chunk by global memory,
// then page allocation
}
}
miss_temp.paddr = paddr;
itlb_miss_buffer[node_id][core_id].push_back(miss_temp);
}
void page_fault_entry_update(int node_id)
{
for (auto it = page_fault_entry[node_id].cbegin(), next_it = it; it != page_fault_entry[node_id].cend(); it = next_it)
{
++next_it;
pair<uint64_t,uint64_t> p = (*it).second;
if (p.second<=common_clock)
{
page_fault_entry[node_id].erase(it);
}
}
}
void itlb_mshr_update(int node_id, int core_id)
{
if (itlb_miss_buffer[node_id][core_id].size() == 1)
{
miss_queue miss_buffer_entry = itlb_miss_buffer[node_id][core_id][0];
if (miss_buffer_entry.complete_cycle == common_clock)
{
uint64_t vaddr = miss_buffer_entry.ins_vaddr;
int proc_id = miss_buffer_entry.inst_fetch.ins.proc_id;
uint64_t paddr = miss_buffer_entry.paddr;
int itlb_id = (node_id * core_count) + core_id;
uint64_t victim_paddr = NULL;
uint64_t victim_vaddr = NULL;
itlbs[itlb_id].ReplaceTLB(vaddr, TLB_BASE::ACCESS_TYPE_LOAD, proc_id, paddr, victim_paddr, victim_vaddr);
itlb_miss_buffer[node_id][core_id].erase(itlb_miss_buffer[node_id][core_id].begin());
}
}
}
void icache_search(int node_id, int core_id, uint64_t cache_access_paddr, uint64_t vaddr, INST_FETCH_QUEUE INST_temp)
{
// search in IL1 Cache
INST inst = INST_temp.ins;
bool il1hit = il1s[core_count * node_id + core_id].AccessSingleCacheLine(cache_access_paddr, CACHE_BASE::ACCESS_TYPE_LOAD, inst.proc_id);
if (il1hit && il1_miss_buffer[node_id][core_id].empty() &&
inst_queue[node_id][core_id].size() < iqueue_size &&
il1_wait_buffer[node_id][core_id].empty())
{
num_icache_hits[node_id][core_id]++;
INST_temp.mem_fetched = true;
INST_temp.mem_complete_cycle = common_clock + L1_HIT; // commom cycle should be added in place of request cycle
if (last_ins_id[node_id][core_id] == core_inst_stream[node_id][core_id].front().ins_id - 1)
{
INST_temp.mem_complete_cycle = common_clock;
inst_queue[node_id][core_id].push(INST_temp);
last_ins_id[node_id][core_id]++;
core_inst_stream[node_id][core_id].pop();
// fetch subsequent instructions in the same block and add to ins_queue
fetch_ins_in_same_block(node_id, core_id, INST_temp);
}
}
else if (!il1hit)
{
miss_queue mshr_temp;
// Add instr in wait/miss buffer and check in L2.
if (il1_miss_buffer[node_id][core_id].size() < mshr)
{
// check present in missbuffer or not. If not present, add in miss_buffer, otherwise in wait_buffer
bool miss_buffer_present = false;
for (auto miss_buffer_entry : il1_miss_buffer[node_id][core_id])
{
// 36 bits same = same page
// next 6 same = same block so 42 bits same
if ((miss_buffer_entry.ins_vaddr & 0xffffffffffc0) == (vaddr & 0xffffffffffc0))
{
miss_buffer_present = true;
mshr_temp = miss_buffer_entry;
}
}
miss_queue miss_new_entry;
miss_new_entry.inst_fetch = INST_temp;
miss_new_entry.ins_id = INST_temp.ins.ins_id;
miss_new_entry.paddr = cache_access_paddr;
miss_new_entry.ins_vaddr = vaddr;
miss_new_entry.node_id = node_id;
miss_new_entry.thread_id = inst.threadid;
miss_new_entry.request_cycle = INST_temp.request_cycle;
miss_new_entry.source_cache = 'I';
miss_new_entry.cache_access_size = 1;
miss_new_entry.core_id = core_id;
miss_new_entry.complete_cycle = -1;
miss_new_entry.write = false;
miss_new_entry.L1_cache_miss_complete_cycle = common_clock + L1_HIT;
if (!miss_buffer_present)
{
num_icache_misses[node_id][core_id]++;
il1_miss_buffer[node_id][core_id].push_back(miss_new_entry);
core_inst_stream[node_id][core_id].pop();
}
else if (miss_buffer_present)
{
// fetch all the subsequent instructions in same block if there and add to wait buffer
get_ins_in_same_block(node_id, core_id, miss_new_entry);
}
}
}
}
// On cache-hit store all the instructions belonging to same cache-line in temp queue
// will be pushed directly to ins_queue if space available, otherwise will be pushed later
void fetch_ins_in_same_block(int node_id, int core_id, INST_FETCH_QUEUE INST_temp)
{
INST temp1 = core_inst_stream[node_id][core_id].front();
uint64_t cur_miss_blockaddr = INST_temp.ins.addr & (0xffffffffffc0);
miss_queue miss_new_entry;
miss_new_entry.inst_fetch = INST_temp;
miss_new_entry.ins_id = INST_temp.ins.ins_id;
while (temp1.addr & (0xffffffffffc0) == cur_miss_blockaddr)
{
INST_temp.ins = temp1;
temp[node_id][core_id].push_back(miss_new_entry);
core_inst_stream[node_id][core_id].pop();
last_ins_id[node_id][core_id]++;
if (!core_inst_stream[node_id][core_id].empty())
{
temp1 = core_inst_stream[node_id][core_id].front();
}
else
break;
}
}
// on cache-miss, if subsequent instructions belong to same block, don't add to mshr,
// rather add to this wait buffer
void get_ins_in_same_block(int node_id, int core_id, miss_queue miss_new_entry)
{
INST temp = core_inst_stream[node_id][core_id].front();
uint64_t cur_miss_blockaddr = (miss_new_entry.ins_vaddr & 0xffffffffffc0);
while ((temp.addr & 0xffffffffffc0) == (cur_miss_blockaddr))
{
miss_new_entry.inst_fetch.ins = temp;
miss_new_entry.ins_vaddr = temp.addr;
miss_new_entry.ins_id = temp.ins_id;
il1_wait_buffer[node_id][core_id].push_back(miss_new_entry);
core_inst_stream[node_id][core_id].pop();
if (!core_inst_stream[node_id][core_id].empty())
temp = core_inst_stream[node_id][core_id].front();
else
break;
}
}
void update_icache_mshr(int node_id, int core_id)
{
// replace the cache entry whenever a hit is completed
if (il1_miss_buffer[node_id][core_id].size() > 0)
if (il1_miss_buffer[node_id][core_id][0].complete_cycle <= common_clock && il1_miss_buffer[node_id][core_id][0].complete_cycle > 0)
il1s[core_count * node_id + core_id].ReplaceCACHE((il1_miss_buffer[node_id][core_id][0]).paddr, CACHE_BASE::ACCESS_TYPE_LOAD, (il1_miss_buffer[node_id][core_id][0]).inst_fetch.ins.proc_id);
// sending fetched instructions from temp queue to ins_queue
// temp queue holds all the instructions belonging to same cache-line
while (!temp[node_id][core_id].empty() && inst_queue[node_id][core_id].size() < iqueue_size)
{
INST_FETCH_QUEUE ins1 = temp[node_id][core_id].front().inst_fetch;
// if(last_ins_id[node_id][core_id]==ins1.ins.ins_id-1)
{
ins1.mem_complete_cycle = common_clock;
inst_queue[node_id][core_id].push(ins1);
temp[node_id][core_id].pop_front();
// last_ins_id[node_id][core_id]++;
}
}
// if still space left in ins_queue, send more fetched instructions from L1-mshr completed enteries
if (inst_queue[node_id][core_id].size() < iqueue_size)
{
// find the mshr entry with completed memory-access
if (!il1_miss_buffer[node_id][core_id].empty())
{
if (il1_miss_buffer[node_id][core_id][0].complete_cycle <= common_clock &&
il1_miss_buffer[node_id][core_id][0].complete_cycle > 0 &&
last_ins_id[node_id][core_id] == il1_miss_buffer[node_id][core_id][0].inst_fetch.ins.ins_id - 1)
{
// push to ins_queue
INST_FETCH_QUEUE ins1 = il1_miss_buffer[node_id][core_id][0].inst_fetch;
last_ins_id[node_id][core_id]++;
ins1.mem_complete_cycle = common_clock;
inst_queue[node_id][core_id].push(ins1);
uint64_t vaddr = il1_miss_buffer[node_id][core_id][0].ins_vaddr;
uint64_t ins_id = il1_miss_buffer[node_id][core_id][0].inst_fetch.ins.ins_id;
il1_miss_buffer[node_id][core_id].erase(il1_miss_buffer[node_id][core_id].begin());
// get all the instruction enteries from the wait buffer that belongs to same cache-line
// a related miss of which is just popped from mshr and pushed to ins_queue
int id=0;
while (!il1_wait_buffer[node_id][core_id].empty() && ((vaddr & 0xffffffffffc0) == (il1_wait_buffer[node_id][core_id][0].ins_vaddr & 0xffffffffffc0)))
{
if (il1_wait_buffer[node_id][core_id][id].ins_id - 1 == last_ins_id[node_id][core_id] && id<il1_wait_buffer[node_id][core_id].size())
{
// cout<<"\nsize"<<il1_wait_buffer[node_id][core_id].size()<<" id"<<id;
// cin.get();
last_ins_id[node_id][core_id]++;
temp[node_id][core_id].push_back(il1_wait_buffer[node_id][core_id][id]);
id++;
// il1_wait_buffer[node_id][core_id].erase(il1_wait_buffer[node_id][core_id].begin());
}
else
{
// cout<<"\nsize ="<<il1_wait_buffer[node_id][core_id].size();
il1_wait_buffer[node_id][core_id].erase(il1_wait_buffer[node_id][core_id].begin(),il1_wait_buffer[node_id][core_id].begin()+id);
// cout<<"\nid="<<id;
// cout<<"\nsize ="<<il1_wait_buffer[node_id][core_id].size();
// cin.get();
break;
}
if (il1_wait_buffer[node_id][core_id].empty())
{
break;
}
}
}
}
}
int64_t tempid = -1;
if (!il1_miss_buffer[node_id][core_id].empty())
{
tempid = il1_miss_buffer[node_id][core_id][0].ins_id;
}
if (last_ins_id[node_id][core_id] + 1 != tempid &&
temp[node_id][core_id].size() < iqueue_size && !il1_wait_buffer[node_id][core_id].empty())
{
if (last_ins_id[node_id][core_id] == il1_wait_buffer[node_id][core_id][0].ins_id - 1)
{
uint64_t tempaddr = il1_wait_buffer[node_id][core_id][0].ins_vaddr;
tempaddr = tempaddr & 0xffffffffffc0;
while ( temp[node_id][core_id].size()<iqueue_size+1000 && tempaddr == (il1_wait_buffer[node_id][core_id][0].ins_vaddr & 0xffffffffffc0))
{
if (last_ins_id[node_id][core_id] == il1_wait_buffer[node_id][core_id][0].ins_id - 1)
{
temp[node_id][core_id].push_back(il1_wait_buffer[node_id][core_id][0]);
il1_wait_buffer[node_id][core_id].erase(il1_wait_buffer[node_id][core_id].begin());
last_ins_id[node_id][core_id]++;
}
else
{
break;
}
if (il1_wait_buffer[node_id][core_id].empty())
{
break;
}
}
}
}
// from newly filled temp to ins_queue if space left in ins_queue, otherwise try next cycle
while (inst_queue[node_id][core_id].size() < iqueue_size && !temp[node_id][core_id].empty())
{
//if(last_ins_id[node_id][core_id]==temp[node_id][core_id].front().ins_id-1)
{
temp[node_id][core_id].front().inst_fetch.mem_complete_cycle = common_clock;
inst_queue[node_id][core_id].push(temp[node_id][core_id].front().inst_fetch);
temp[node_id][core_id].pop_front();
// last_ins_id[node_id][core_id]++;
}
// else
// break;
}
}
bool dtlb_to_dcache[num_nodes][core_count] = {0};
void dtlb_search(int node_id, int core_id)
{
if (branch_misprediction_penalty[node_id][core_id] > 0)
{
return;
}
miss_queue load_store_entry;
if (!load_store_buffer[node_id][core_id].empty())
{
load_store_entry = load_store_buffer[node_id][core_id].front();
}
else
return;
uint64_t vaddr = load_store_entry.ins_vaddr;
uint64_t paddr = NULL;
int dtlb_id = (node_id * core_count) + core_id;
bool dtlb_hit = false;
dtlb_hit = dtlbs[dtlb_id].AccessTLB(vaddr, TLB_BASE::ACCESS_TYPE_LOAD, load_store_entry.inst_fetch.ins.proc_id, paddr);
load_store_entry.paddr = paddr;
if (dtlb_hit)
{
if (dtlb_to_dcache[node_id][core_id])
{
dtlb_to_dcache[node_id][core_id] = 0;
return;
}
// if dtlb hit get the physical address from TLB and pass to cache
uint64_t vaddr_offset = vaddr & 0xfff;
paddr = paddr << 12;
uint64_t cache_access_paddr = paddr + vaddr_offset;
load_store_entry.inst_fetch.request_cycle = common_clock;
load_store_entry.inst_fetch.tlb_complete_cycle = common_clock + TLB_HIT;
load_store_entry.inst_fetch.tlb_fetched = true;
// access dcache n case of dtlb hit
bool dl1hit = dcache_hit(node_id, core_id, cache_access_paddr, vaddr, load_store_entry, 1);
if (!dl1hit)
{
if (dl1_miss_buffer[node_id][core_id].size() < mshr)
{
dcache_miss(node_id, core_id, cache_access_paddr, vaddr, load_store_entry);
load_store_buffer[node_id][core_id].pop();
}
}
}
else
{
for (auto i = 0; i < dtlb_miss_buffer[node_id][core_id].size(); i++)
{
if ((vaddr & 0xfffffffff000) == (dtlb_miss_buffer[node_id][core_id][i].ins_vaddr & 0xfffffffff000))
{
return;
}
}
if (dtlb_miss_buffer[node_id][core_id].size() < mshr)
{
load_store_entry.request_cycle = common_clock;
DTLB_MISS(load_store_entry, node_id, core_id);
}
}
}
void DTLB_MISS(miss_queue &miss_temp, int node_id, int core_id)
{
uint64_t vaddr = miss_temp.ins_vaddr;
uint64_t paddr = NULL;
bool page_found_in_page_table = false;
uint64_t temp_vaddr = vaddr>>12;
if(page_fault_entry[node_id].find(temp_vaddr) != page_fault_entry[node_id].end())
{
pair<uint64_t,uint64_t> p = page_fault_entry[node_id][temp_vaddr];
miss_temp.paddr = p.first;
miss_temp.complete_cycle = p.second;
dtlb_miss_buffer[node_id][core_id].push_back(miss_temp);
load_store_buffer[node_id][core_id].pop();
return;
}
page_found_in_page_table = page_table_walk(_pgd[node_id], vaddr, paddr);
if (page_found_in_page_table)
{
miss_temp.complete_cycle = miss_temp.request_cycle + TLB_MISS;
}
else
{
bool new_remote_chunk_allocated = false;
handle_page_fault(_pgd[node_id], node_id, vaddr, paddr, L[node_id], new_remote_chunk_allocated); // handle by allocating a new page in Local or Remote
if (new_remote_chunk_allocated == false)
miss_temp.complete_cycle = miss_temp.request_cycle + page_fault_latency; // page_fault complete after 9ms if free page (local/remote) is there
else
{
// if we are allocating remote page and remote memory is not available,
miss_temp.complete_cycle = miss_temp.request_cycle + chunk_allocation_plus_page_fault_latency; // add 25ms, first 16ns to allocate a remote memory chunk by global memory,
// then page allocation
}
}
miss_temp.paddr = paddr;
dtlb_miss_buffer[node_id][core_id].push_back(miss_temp);
load_store_buffer[node_id][core_id].pop();
}
void dtlb_mshr_update(int node_id, int core_id)
{
for (auto i = dtlb_miss_buffer[node_id][core_id].begin(); i != dtlb_miss_buffer[node_id][core_id].end(); i++)
{
miss_queue miss_buffer_entry = (*i);
if (miss_buffer_entry.complete_cycle <= common_clock)
{
uint64_t vaddr = miss_buffer_entry.ins_vaddr;
int proc_id = miss_buffer_entry.inst_fetch.ins.proc_id;
uint64_t paddr = miss_buffer_entry.paddr;
int dtlb_id = (node_id * core_count) + core_id;
uint64_t victim_paddr = NULL;
uint64_t victim_vaddr = NULL;
dtlbs[dtlb_id].ReplaceTLB(vaddr, TLB_BASE::ACCESS_TYPE_LOAD, proc_id, paddr, victim_paddr, victim_vaddr);
miss_buffer_entry.inst_fetch.tlb_complete_cycle = common_clock + TLB_HIT;
miss_buffer_entry.inst_fetch.tlb_fetched = true;
uint64_t vaddr_offset = vaddr & 0xfff;
paddr = paddr << 12;
uint64_t cache_access_paddr = paddr + vaddr_offset;
bool dl1hit = dcache_hit(node_id, core_id, cache_access_paddr, vaddr, miss_buffer_entry, 0);
if (!dl1hit)
{
if (dl1_miss_buffer[node_id][core_id].size() < mshr)
{
dcache_miss(node_id, core_id, cache_access_paddr, vaddr, miss_buffer_entry);
dtlb_miss_buffer[node_id][core_id].erase(i);
}
}
else
{
dtlb_miss_buffer[node_id][core_id].erase(i);
}
dtlb_to_dcache[node_id][core_id] = 1;
break;
}
}
}
bool dcache_hit(int node_id, int core_id, uint64_t cache_access_paddr, uint64_t vaddr, miss_queue &load_store_entry, int source)
{
bool dl1hit = false;
load_store_entry.source_cache = 'D';
CACHE_BASE::ACCESS_TYPE acctype = CACHE_BASE::ACCESS_TYPE_LOAD;
if (load_store_entry.write)
{
acctype = CACHE_BASE::ACCESS_TYPE_STORE;
}
if (load_store_entry.cache_access_size > 4)
{
int line_read = 0;
bool line_hit[2];
dl1hit = dl1s[core_count * node_id + core_id].AccessMultiCacheLine(cache_access_paddr,
load_store_entry.cache_access_size, acctype, load_store_entry.inst_fetch.ins.proc_id,
line_read, line_hit);
}
else
{
dl1hit = dl1s[core_count * node_id + core_id].AccessSingleCacheLine(cache_access_paddr, acctype, load_store_entry.inst_fetch.ins.proc_id);
}
if (dl1hit)
{
num_dcache_hits[node_id][core_id]++;
load_store_entry.complete_cycle = common_clock + L1_HIT;
response_queue[node_id][core_id].push(load_store_entry);
if (source == 1)
load_store_buffer[node_id][core_id].pop();
}
return dl1hit;
}
void dcache_miss(int node_id, int core_id, uint64_t cache_access_paddr, uint64_t vaddr, miss_queue load_store_entry)
{
num_dcache_misses[node_id][core_id]++;
load_store_entry.source_cache = 'D';
for (auto it = dl1_miss_buffer[node_id][core_id].begin(); it != dl1_miss_buffer[node_id][core_id].end(); it++)
{
if((vaddr>>6) == (*it).ins_vaddr>>6)
{
(*it).ld_str_dest.push_back(load_store_entry.ins_id);
return;
}
}
// to check
load_store_entry.request_cycle = common_clock;
load_store_entry.complete_cycle = -1;
load_store_entry.L1_cache_miss_complete_cycle = common_clock + L1_HIT;
load_store_entry.paddr = cache_access_paddr;
dl1_miss_buffer[node_id][core_id].push_back(load_store_entry);
}
void update_dcache_mshr(int node_id, int core_id)
{
// removing completed mshr enteries and replacing the victim cache blocks with new blocks and performing write-back
// if modified block is replaced
for (auto it = dl1_miss_buffer[node_id][core_id].begin(); it != dl1_miss_buffer[node_id][core_id].end(); it++)
{
if ((*it).complete_cycle <= common_clock && (*it).complete_cycle > 0)
{
int line_read = 0;
miss_queue load_store_entry = (*it);
bool line_hit[2];
CACHE_BASE::ACCESS_TYPE acctype = CACHE_BASE::ACCESS_TYPE_LOAD;
if (load_store_entry.write)
acctype = CACHE_BASE::ACCESS_TYPE_STORE;
uint64_t paddr = (*it).paddr;
dl1s[core_count * node_id + core_id].AccessMultiCacheLine(paddr, load_store_entry.cache_access_size, acctype, load_store_entry.inst_fetch.ins.proc_id, line_read, line_hit);
// no block present simply replace and get the corresponding victim
for (int i = 0; i < line_read; i++)
{
if (line_hit[i] == 0)
{
// address of the victim block to write back to memory
uint64_t victim_addr = NULL;
bool victim_modified = dl1s[core_count * node_id + core_id].ReplaceCACHE(paddr, acctype, (*it).inst_fetch.ins.proc_id, victim_addr);
if (victim_modified)
{
int cache_level = 1; // cache level from which write-back should happen
// need address of replaced block
perform_write_back(node_id, core_id, cache_level, (*it).inst_fetch.ins.proc_id, victim_addr, acctype);
}
GetNextBlockAddress(paddr, (*it).inst_fetch.ins.proc_id);
}
}
for(auto k: (*it).ld_str_dest)
{
broadcast_completed_LSQ(node_id, core_id,k);
// num_dcache_misses[node_id][core_id]++;
}
broadcast_completed_LSQ(node_id, core_id, (*it).ins_id);
num_unique_dcache_misses[node_id][core_id]++;
dl1_miss_buffer[node_id][core_id].erase(it);
if (dl1_miss_buffer[node_id][core_id].empty() || it == dl1_miss_buffer[node_id][core_id].end())
{
break;
}
}
}
}
// selecting the source mshr (I/D) while adding a pending entry to L2-mshr on L2 miss
int cache_source[num_nodes][core_count] = {1}; // 0 for I-cache, 1 for D-cache
void update_l2_mshr(int node_id, int core_id)
{
// checking the completion of miss requests in the icache/dcache and start L2 cache search
// if hit in L2, update completion time in the dcache, otherwise put in L2-mshr
CACHE_BASE::ACCESS_TYPE acctype = CACHE_BASE::ACCESS_TYPE_LOAD;
for (int i = 0; i < 2; i++)
{
cache_source[node_id][core_id] = (cache_source[node_id][core_id] + 1) % 2;
switch (cache_source[node_id][core_id])
{
case 0:
if (il1_miss_buffer[node_id][core_id].size() > 0)
{
for (auto it = il1_miss_buffer[node_id][core_id].begin(); it != il1_miss_buffer[node_id][core_id].end(); it++)
{
miss_queue load_store_entry = (*it);
if ((*it).L1_cache_miss_complete_cycle <= common_clock && (*it).L1_cache_miss_complete_cycle > 0)
{
(*it).L1_cache_miss_complete_cycle = 0;
bool l2hit = l2s[core_count * node_id + core_id].AccessSingleCacheLine((*it).paddr,
acctype, (*it).inst_fetch.ins.proc_id);
num_l2_access[node_id][core_id]++;
if (l2hit)
{
num_l2_hits[node_id][core_id]++;
(*it).complete_cycle = common_clock + L2_HIT;
break;
}
else
{
(*it).L2_cache_miss_complete_cycle = common_clock + L2_HIT;
l2_miss_buffer[node_id][core_id].push_back((*it));
break;
}
}
}
}
break;
case 1:
if (dl1_miss_buffer[node_id][core_id].size() > 0)
{
for (auto it = dl1_miss_buffer[node_id][core_id].begin(); it != dl1_miss_buffer[node_id][core_id].end(); it++)
{
miss_queue load_store_entry = (*it);
if ((*it).L1_cache_miss_complete_cycle <= common_clock && (*it).L1_cache_miss_complete_cycle > 0)
{
(*it).L1_cache_miss_complete_cycle = 0;
int line_read = 0;
bool line_hit[2];
if (load_store_entry.write)
acctype = CACHE_BASE::ACCESS_TYPE_STORE;
bool l2hit = l2s[core_count * node_id + core_id].AccessMultiCacheLine(load_store_entry.paddr,
load_store_entry.cache_access_size, acctype, load_store_entry.inst_fetch.ins.proc_id,
line_read, line_hit);
num_l2_access[node_id][core_id]++;
if (l2hit)
{
num_l2_hits[node_id][core_id]++;
(*it).complete_cycle = common_clock + L2_HIT;
break;
}
else
{
(*it).L2_cache_miss_complete_cycle = common_clock + L2_HIT;
l2_miss_buffer[node_id][core_id].push_back((*it));
break;
}
}
}
}
break;
}
}
cache_source[node_id][core_id] = (cache_source[node_id][core_id] + 1) % 2;
// removing from l2-mshr whenever a pending miss completes
for (auto it = l2_miss_buffer[node_id][core_id].begin(); it != l2_miss_buffer[node_id][core_id].end(); ++it)
{
auto miss_buffer_entry = (*it);
// Replace the cache entery after a hit completes
if (miss_buffer_entry.complete_cycle <= common_clock && miss_buffer_entry.complete_cycle > 0)
{
int line_read = 0;
bool line_hit[2];
CACHE_BASE::ACCESS_TYPE acctype = CACHE_BASE::ACCESS_TYPE_LOAD;
if ((*it).write)
acctype = CACHE_BASE::ACCESS_TYPE_STORE;
uint64_t paddr = (*it).paddr;
miss_queue load_store_entry = (*it);
l2s[core_count * node_id + core_id].AccessMultiCacheLine(paddr, load_store_entry.cache_access_size,
acctype, load_store_entry.inst_fetch.ins.proc_id, line_read, line_hit);
// no block present, simply replace and get the corresponding victim
for (int i = 0; i < line_read; i++)
{
if (line_hit[i] == 0)
{
// address of the victim block to write back to memory
uint64_t victim_addr = NULL;
bool victim_modified = l2s[core_count * node_id + core_id].ReplaceCACHE(paddr, acctype, (*it).inst_fetch.ins.proc_id, victim_addr);
if (victim_modified)
{
int cache_level = 2; // cache level from which write-back should happen
// need address of replaced block
perform_write_back(node_id, core_id, cache_level, (*it).inst_fetch.ins.proc_id, victim_addr, acctype);
}
GetNextBlockAddress(paddr, (*it).inst_fetch.ins.proc_id);
}
}
l2_miss_buffer[node_id][core_id].erase(it);