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Open Logic FPGA Standard Library

VHDL 523 52 Updated Feb 21, 2025

The USRP™ Hardware Driver Repository

Verilog 1,053 679 Updated Feb 17, 2025

Example applications for UHD/RFNoC

C++ 13 2 Updated Mar 8, 2022

Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.

C 61 39 Updated Feb 18, 2025

RFSoC QSFP Data Offload Design with GNU Radio

Tcl 17 9 Updated Nov 21, 2024

PlutoSDR Firmware

Shell 355 205 Updated Oct 15, 2024

Linux kernel variant from Analog Devices; see README.md for details

C 488 863 Updated Mar 5, 2025

Repository of antsdr firmware make

Shell 59 25 Updated Jan 21, 2025

The official Linux kernel from Xilinx

C 1,403 1,542 Updated Feb 26, 2025

Linux device tree generator for the Xilinx SDK (Vivado > 2014.1)

Tcl 209 196 Updated Nov 15, 2024

A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).

Jupyter Notebook 23 6 Updated Jun 22, 2023

Python productivity for RFSoC platforms

Jupyter Notebook 63 29 Updated May 21, 2024

The USRP™ Hardware Driver FPGA Repository

Verilog 278 206 Updated Dec 13, 2021

HDL libraries and projects

Verilog 1,594 1,543 Updated Mar 5, 2025

Software drivers in C for systems without an operating system

C 1,048 1,693 Updated Mar 5, 2025

Verilog PCI express components

Verilog 1,234 323 Updated Apr 26, 2024

Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

Batchfile 535 106 Updated Sep 14, 2023

Exablaze High Rate Capture Software

C 25 14 Updated Aug 14, 2023

Open source FPGA-based NIC and platform for in-network compute

Verilog 1,822 434 Updated Jul 5, 2024

SPI Master for FPGA - VHDL and Verilog

VHDL 271 97 Updated Aug 22, 2023

SDIO Device Verilog Core

Verilog 22 14 Updated Jul 25, 2018

VHDL implementation for configuration of the SI5338 with an I2C master in VHDL with separate parser for using the configuration file from ClockBuilder.

VHDL 5 5 Updated Jan 13, 2015

Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks

Tcl 63 32 Updated Nov 21, 2024

Standalone application based on ADI hdl and no_OS for ANTSDR.

C 21 13 Updated Aug 11, 2023
Verilog 129 67 Updated Apr 24, 2015

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

C++ 791 279 Updated Nov 17, 2024

GNU Radio decoder for Amateur satellites

Jupyter Notebook 813 170 Updated Mar 4, 2025

🌊 Digital timing diagram rendering engine

JavaScript 3,088 376 Updated Jan 29, 2025
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