KVM: ioapic: clear IRR for edge-triggered interrupts at delivery

This ensures that IRR bits are set in the KVM_GET_IRQCHIP result only if the interrupt is still sitting in the IOAPIC. After the next patches, it avoids spurious reinjection of the interrupt when KVM_SET_IRQCHIP is called. Reviewed-by: Alex Williamson <[email protected]> Signed-off-by: Paolo Bonzini <[email protected]>
Baughn · Mar 21, 2014 · 0bc830b · 0bc830b
1 parent 0b10a1c
commit 0bc830b
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/virt/kvm/ioapic.c b/virt/kvm/ioapic.c
@@ -288,6 +288,9 @@ static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status)
 	irqe.level = 1;
 	irqe.shorthand = 0;
 
+	if (irqe.trig_mode == IOAPIC_EDGE_TRIG)
+		ioapic->irr &= ~(1 << irq);
+
 	if (irq == RTC_GSI && line_status) {
 		BUG_ON(ioapic->rtc_status.pending_eoi != 0);
 		ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe,