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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upst…
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…ream-linus

Pull MIPS fixes from Ralf Baechle:
 "This is dominated by a large number of changes necessary for the MIPS
  BPF code.  code.  Aside of that there are

   - a fix for the MSC system controller support code.
   - a Turbochannel fix.
   - a recordmcount fix that's MIPS-specific.
   - barrier fixes to smp-cps / pm-cps after unrelated changes elsewhere
     in the kernel.
   - revert support for MSA registers in the signal frames.  The
     reverted patch did modify the signal stack frame which of course is
     inacceptable.
   - fix math-emu build breakage with older compilers.
   - some related cleanup.
   - fix Lasat build error if CONFIG_CRC32 isn't set to y by the user"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (27 commits)
  MIPS: Lasat: Fix build error if CRC32 is not enabled.
  TC: Handle device_register() errors.
  MIPS: MSC: Prevent out-of-bounds writes to MIPS SC ioremap'd region
  MIPS: bpf: Fix stack space allocation for BPF memwords on MIPS64
  MIPS: BPF: Use 32 or 64-bit load instruction to load an address to register
  MIPS: bpf: Fix PKT_TYPE case for big-endian cores
  MIPS: BPF: Prevent kernel fall over for >=32bit shifts
  MIPS: bpf: Drop update_on_xread and always initialize the X register
  MIPS: bpf: Fix is_range() semantics
  MIPS: bpf: Use pr_debug instead of pr_warn for unhandled opcodes
  MIPS: bpf: Fix return values for VLAN_TAG_PRESENT case
  MIPS: bpf: Use correct mask for VLAN_TAG case
  MIPS: bpf: Fix branch conditional for BPF_J{GT/GE} cases
  MIPS: bpf: Add SEEN_SKB to flags when looking for the PKT_TYPE
  MIPS: bpf: Use 'andi' instead of 'and' for the VLAN cases
  MIPS: bpf: Return error code if the offset is a negative number
  MIPS: bpf: Use the LO register to get division's quotient
  MIPS: mm: uasm: Fix lh micro-assembler instruction
  MIPS: uasm: Add SLT uasm instruction
  MIPS: uasm: Add s3s1s2 instruction builder
  ...
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@torvalds
torvalds committed Jun 28, 2014
2 parents 1857a5b + 16f0bbb commit c9a6066
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Showing 19 changed files with 211 additions and 499 deletions.
1 change: 1 addition & 0 deletions arch/mips/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -269,6 +269,7 @@ config LANTIQ
config LASAT
bool "LASAT Networks platforms"
select CEVT_R4K
select CRC32
select CSRC_R4K
select DMA_NONCOHERENT
select SYS_HAS_EARLY_PRINTK
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2 changes: 0 additions & 2 deletions arch/mips/include/asm/sigcontext.h
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Original file line number Diff line number Diff line change
Expand Up @@ -32,8 +32,6 @@ struct sigcontext32 {
__u32 sc_lo2;
__u32 sc_hi3;
__u32 sc_lo3;
__u64 sc_msaregs[32]; /* Most significant 64 bits */
__u32 sc_msa_csr;
};
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
#endif /* _ASM_SIGCONTEXT_H */
4 changes: 4 additions & 0 deletions arch/mips/include/asm/uasm.h
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Original file line number Diff line number Diff line change
Expand Up @@ -67,6 +67,9 @@ void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
#define Ip_u2s3u1(op) \
void ISAOPC(op)(u32 **buf, unsigned int a, signed int b, unsigned int c)

#define Ip_s3s1s2(op) \
void ISAOPC(op)(u32 **buf, int a, int b, int c)

#define Ip_u2u1s3(op) \
void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)

Expand Down Expand Up @@ -147,6 +150,7 @@ Ip_u2s3u1(_scd);
Ip_u2s3u1(_sd);
Ip_u2u1u3(_sll);
Ip_u3u2u1(_sllv);
Ip_s3s1s2(_slt);
Ip_u2u1s3(_sltiu);
Ip_u3u1u2(_sltu);
Ip_u2u1u3(_sra);
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1 change: 1 addition & 0 deletions arch/mips/include/uapi/asm/inst.h
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Original file line number Diff line number Diff line change
Expand Up @@ -273,6 +273,7 @@ enum mm_32a_minor_op {
mm_and_op = 0x250,
mm_or32_op = 0x290,
mm_xor32_op = 0x310,
mm_slt_op = 0x350,
mm_sltu_op = 0x390,
};

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8 changes: 0 additions & 8 deletions arch/mips/include/uapi/asm/sigcontext.h
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Original file line number Diff line number Diff line change
Expand Up @@ -12,10 +12,6 @@
#include <linux/types.h>
#include <asm/sgidefs.h>

/* Bits which may be set in sc_used_math */
#define USEDMATH_FP (1 << 0)
#define USEDMATH_MSA (1 << 1)

#if _MIPS_SIM == _MIPS_SIM_ABI32

/*
Expand All @@ -41,8 +37,6 @@ struct sigcontext {
unsigned long sc_lo2;
unsigned long sc_hi3;
unsigned long sc_lo3;
unsigned long long sc_msaregs[32]; /* Most significant 64 bits */
unsigned long sc_msa_csr;
};

#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
Expand Down Expand Up @@ -76,8 +70,6 @@ struct sigcontext {
__u32 sc_used_math;
__u32 sc_dsp;
__u32 sc_reserved;
__u64 sc_msaregs[32];
__u32 sc_msa_csr;
};


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3 changes: 0 additions & 3 deletions arch/mips/kernel/asm-offsets.c
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Original file line number Diff line number Diff line change
Expand Up @@ -293,7 +293,6 @@ void output_sc_defines(void)
OFFSET(SC_LO2, sigcontext, sc_lo2);
OFFSET(SC_HI3, sigcontext, sc_hi3);
OFFSET(SC_LO3, sigcontext, sc_lo3);
OFFSET(SC_MSAREGS, sigcontext, sc_msaregs);
BLANK();
}
#endif
Expand All @@ -308,7 +307,6 @@ void output_sc_defines(void)
OFFSET(SC_MDLO, sigcontext, sc_mdlo);
OFFSET(SC_PC, sigcontext, sc_pc);
OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
OFFSET(SC_MSAREGS, sigcontext, sc_msaregs);
BLANK();
}
#endif
Expand All @@ -320,7 +318,6 @@ void output_sc32_defines(void)
OFFSET(SC32_FPREGS, sigcontext32, sc_fpregs);
OFFSET(SC32_FPC_CSR, sigcontext32, sc_fpc_csr);
OFFSET(SC32_FPC_EIR, sigcontext32, sc_fpc_eir);
OFFSET(SC32_MSAREGS, sigcontext32, sc_msaregs);
BLANK();
}
#endif
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2 changes: 1 addition & 1 deletion arch/mips/kernel/irq-msc01.c
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Original file line number Diff line number Diff line change
Expand Up @@ -126,7 +126,7 @@ void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqma

board_bind_eic_interrupt = &msc_bind_eic_interrupt;

for (; nirq >= 0; nirq--, imp++) {
for (; nirq > 0; nirq--, imp++) {
int n = imp->im_irq;

switch (imp->im_type) {
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4 changes: 2 additions & 2 deletions arch/mips/kernel/pm-cps.c
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Original file line number Diff line number Diff line change
Expand Up @@ -101,7 +101,7 @@ static void coupled_barrier(atomic_t *a, unsigned online)
if (!coupled_coherence)
return;

smp_mb__before_atomic_inc();
smp_mb__before_atomic();
atomic_inc(a);

while (atomic_read(a) < online)
Expand Down Expand Up @@ -158,7 +158,7 @@ int cps_pm_enter_state(enum cps_pm_state state)

/* Indicate that this CPU might not be coherent */
cpumask_clear_cpu(cpu, &cpu_coherent_mask);
smp_mb__after_clear_bit();
smp_mb__after_atomic();

/* Create a non-coherent mapping of the core ready_count */
core_ready_count = per_cpu(ready_count, core);
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213 changes: 0 additions & 213 deletions arch/mips/kernel/r4k_fpu.S
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,6 @@
* Copyright (C) 1999, 2001 Silicon Graphics, Inc.
*/
#include <asm/asm.h>
#include <asm/asmmacro.h>
#include <asm/errno.h>
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
Expand Down Expand Up @@ -246,218 +245,6 @@ LEAF(_restore_fp_context32)
END(_restore_fp_context32)
#endif

#ifdef CONFIG_CPU_HAS_MSA

.macro save_sc_msareg wr, off, sc, tmp
#ifdef CONFIG_64BIT
copy_u_d \tmp, \wr, 1
EX sd \tmp, (\off+(\wr*8))(\sc)
#elif defined(CONFIG_CPU_LITTLE_ENDIAN)
copy_u_w \tmp, \wr, 2
EX sw \tmp, (\off+(\wr*8)+0)(\sc)
copy_u_w \tmp, \wr, 3
EX sw \tmp, (\off+(\wr*8)+4)(\sc)
#else /* CONFIG_CPU_BIG_ENDIAN */
copy_u_w \tmp, \wr, 2
EX sw \tmp, (\off+(\wr*8)+4)(\sc)
copy_u_w \tmp, \wr, 3
EX sw \tmp, (\off+(\wr*8)+0)(\sc)
#endif
.endm

/*
* int _save_msa_context(struct sigcontext *sc)
*
* Save the upper 64 bits of each vector register along with the MSA_CSR
* register into sc. Returns zero on success, else non-zero.
*/
LEAF(_save_msa_context)
save_sc_msareg 0, SC_MSAREGS, a0, t0
save_sc_msareg 1, SC_MSAREGS, a0, t0
save_sc_msareg 2, SC_MSAREGS, a0, t0
save_sc_msareg 3, SC_MSAREGS, a0, t0
save_sc_msareg 4, SC_MSAREGS, a0, t0
save_sc_msareg 5, SC_MSAREGS, a0, t0
save_sc_msareg 6, SC_MSAREGS, a0, t0
save_sc_msareg 7, SC_MSAREGS, a0, t0
save_sc_msareg 8, SC_MSAREGS, a0, t0
save_sc_msareg 9, SC_MSAREGS, a0, t0
save_sc_msareg 10, SC_MSAREGS, a0, t0
save_sc_msareg 11, SC_MSAREGS, a0, t0
save_sc_msareg 12, SC_MSAREGS, a0, t0
save_sc_msareg 13, SC_MSAREGS, a0, t0
save_sc_msareg 14, SC_MSAREGS, a0, t0
save_sc_msareg 15, SC_MSAREGS, a0, t0
save_sc_msareg 16, SC_MSAREGS, a0, t0
save_sc_msareg 17, SC_MSAREGS, a0, t0
save_sc_msareg 18, SC_MSAREGS, a0, t0
save_sc_msareg 19, SC_MSAREGS, a0, t0
save_sc_msareg 20, SC_MSAREGS, a0, t0
save_sc_msareg 21, SC_MSAREGS, a0, t0
save_sc_msareg 22, SC_MSAREGS, a0, t0
save_sc_msareg 23, SC_MSAREGS, a0, t0
save_sc_msareg 24, SC_MSAREGS, a0, t0
save_sc_msareg 25, SC_MSAREGS, a0, t0
save_sc_msareg 26, SC_MSAREGS, a0, t0
save_sc_msareg 27, SC_MSAREGS, a0, t0
save_sc_msareg 28, SC_MSAREGS, a0, t0
save_sc_msareg 29, SC_MSAREGS, a0, t0
save_sc_msareg 30, SC_MSAREGS, a0, t0
save_sc_msareg 31, SC_MSAREGS, a0, t0
jr ra
li v0, 0
END(_save_msa_context)

#ifdef CONFIG_MIPS32_COMPAT

/*
* int _save_msa_context32(struct sigcontext32 *sc)
*
* Save the upper 64 bits of each vector register along with the MSA_CSR
* register into sc. Returns zero on success, else non-zero.
*/
LEAF(_save_msa_context32)
save_sc_msareg 0, SC32_MSAREGS, a0, t0
save_sc_msareg 1, SC32_MSAREGS, a0, t0
save_sc_msareg 2, SC32_MSAREGS, a0, t0
save_sc_msareg 3, SC32_MSAREGS, a0, t0
save_sc_msareg 4, SC32_MSAREGS, a0, t0
save_sc_msareg 5, SC32_MSAREGS, a0, t0
save_sc_msareg 6, SC32_MSAREGS, a0, t0
save_sc_msareg 7, SC32_MSAREGS, a0, t0
save_sc_msareg 8, SC32_MSAREGS, a0, t0
save_sc_msareg 9, SC32_MSAREGS, a0, t0
save_sc_msareg 10, SC32_MSAREGS, a0, t0
save_sc_msareg 11, SC32_MSAREGS, a0, t0
save_sc_msareg 12, SC32_MSAREGS, a0, t0
save_sc_msareg 13, SC32_MSAREGS, a0, t0
save_sc_msareg 14, SC32_MSAREGS, a0, t0
save_sc_msareg 15, SC32_MSAREGS, a0, t0
save_sc_msareg 16, SC32_MSAREGS, a0, t0
save_sc_msareg 17, SC32_MSAREGS, a0, t0
save_sc_msareg 18, SC32_MSAREGS, a0, t0
save_sc_msareg 19, SC32_MSAREGS, a0, t0
save_sc_msareg 20, SC32_MSAREGS, a0, t0
save_sc_msareg 21, SC32_MSAREGS, a0, t0
save_sc_msareg 22, SC32_MSAREGS, a0, t0
save_sc_msareg 23, SC32_MSAREGS, a0, t0
save_sc_msareg 24, SC32_MSAREGS, a0, t0
save_sc_msareg 25, SC32_MSAREGS, a0, t0
save_sc_msareg 26, SC32_MSAREGS, a0, t0
save_sc_msareg 27, SC32_MSAREGS, a0, t0
save_sc_msareg 28, SC32_MSAREGS, a0, t0
save_sc_msareg 29, SC32_MSAREGS, a0, t0
save_sc_msareg 30, SC32_MSAREGS, a0, t0
save_sc_msareg 31, SC32_MSAREGS, a0, t0
jr ra
li v0, 0
END(_save_msa_context32)

#endif /* CONFIG_MIPS32_COMPAT */

.macro restore_sc_msareg wr, off, sc, tmp
#ifdef CONFIG_64BIT
EX ld \tmp, (\off+(\wr*8))(\sc)
insert_d \wr, 1, \tmp
#elif defined(CONFIG_CPU_LITTLE_ENDIAN)
EX lw \tmp, (\off+(\wr*8)+0)(\sc)
insert_w \wr, 2, \tmp
EX lw \tmp, (\off+(\wr*8)+4)(\sc)
insert_w \wr, 3, \tmp
#else /* CONFIG_CPU_BIG_ENDIAN */
EX lw \tmp, (\off+(\wr*8)+4)(\sc)
insert_w \wr, 2, \tmp
EX lw \tmp, (\off+(\wr*8)+0)(\sc)
insert_w \wr, 3, \tmp
#endif
.endm

/*
* int _restore_msa_context(struct sigcontext *sc)
*/
LEAF(_restore_msa_context)
restore_sc_msareg 0, SC_MSAREGS, a0, t0
restore_sc_msareg 1, SC_MSAREGS, a0, t0
restore_sc_msareg 2, SC_MSAREGS, a0, t0
restore_sc_msareg 3, SC_MSAREGS, a0, t0
restore_sc_msareg 4, SC_MSAREGS, a0, t0
restore_sc_msareg 5, SC_MSAREGS, a0, t0
restore_sc_msareg 6, SC_MSAREGS, a0, t0
restore_sc_msareg 7, SC_MSAREGS, a0, t0
restore_sc_msareg 8, SC_MSAREGS, a0, t0
restore_sc_msareg 9, SC_MSAREGS, a0, t0
restore_sc_msareg 10, SC_MSAREGS, a0, t0
restore_sc_msareg 11, SC_MSAREGS, a0, t0
restore_sc_msareg 12, SC_MSAREGS, a0, t0
restore_sc_msareg 13, SC_MSAREGS, a0, t0
restore_sc_msareg 14, SC_MSAREGS, a0, t0
restore_sc_msareg 15, SC_MSAREGS, a0, t0
restore_sc_msareg 16, SC_MSAREGS, a0, t0
restore_sc_msareg 17, SC_MSAREGS, a0, t0
restore_sc_msareg 18, SC_MSAREGS, a0, t0
restore_sc_msareg 19, SC_MSAREGS, a0, t0
restore_sc_msareg 20, SC_MSAREGS, a0, t0
restore_sc_msareg 21, SC_MSAREGS, a0, t0
restore_sc_msareg 22, SC_MSAREGS, a0, t0
restore_sc_msareg 23, SC_MSAREGS, a0, t0
restore_sc_msareg 24, SC_MSAREGS, a0, t0
restore_sc_msareg 25, SC_MSAREGS, a0, t0
restore_sc_msareg 26, SC_MSAREGS, a0, t0
restore_sc_msareg 27, SC_MSAREGS, a0, t0
restore_sc_msareg 28, SC_MSAREGS, a0, t0
restore_sc_msareg 29, SC_MSAREGS, a0, t0
restore_sc_msareg 30, SC_MSAREGS, a0, t0
restore_sc_msareg 31, SC_MSAREGS, a0, t0
jr ra
li v0, 0
END(_restore_msa_context)

#ifdef CONFIG_MIPS32_COMPAT

/*
* int _restore_msa_context32(struct sigcontext32 *sc)
*/
LEAF(_restore_msa_context32)
restore_sc_msareg 0, SC32_MSAREGS, a0, t0
restore_sc_msareg 1, SC32_MSAREGS, a0, t0
restore_sc_msareg 2, SC32_MSAREGS, a0, t0
restore_sc_msareg 3, SC32_MSAREGS, a0, t0
restore_sc_msareg 4, SC32_MSAREGS, a0, t0
restore_sc_msareg 5, SC32_MSAREGS, a0, t0
restore_sc_msareg 6, SC32_MSAREGS, a0, t0
restore_sc_msareg 7, SC32_MSAREGS, a0, t0
restore_sc_msareg 8, SC32_MSAREGS, a0, t0
restore_sc_msareg 9, SC32_MSAREGS, a0, t0
restore_sc_msareg 10, SC32_MSAREGS, a0, t0
restore_sc_msareg 11, SC32_MSAREGS, a0, t0
restore_sc_msareg 12, SC32_MSAREGS, a0, t0
restore_sc_msareg 13, SC32_MSAREGS, a0, t0
restore_sc_msareg 14, SC32_MSAREGS, a0, t0
restore_sc_msareg 15, SC32_MSAREGS, a0, t0
restore_sc_msareg 16, SC32_MSAREGS, a0, t0
restore_sc_msareg 17, SC32_MSAREGS, a0, t0
restore_sc_msareg 18, SC32_MSAREGS, a0, t0
restore_sc_msareg 19, SC32_MSAREGS, a0, t0
restore_sc_msareg 20, SC32_MSAREGS, a0, t0
restore_sc_msareg 21, SC32_MSAREGS, a0, t0
restore_sc_msareg 22, SC32_MSAREGS, a0, t0
restore_sc_msareg 23, SC32_MSAREGS, a0, t0
restore_sc_msareg 24, SC32_MSAREGS, a0, t0
restore_sc_msareg 25, SC32_MSAREGS, a0, t0
restore_sc_msareg 26, SC32_MSAREGS, a0, t0
restore_sc_msareg 27, SC32_MSAREGS, a0, t0
restore_sc_msareg 28, SC32_MSAREGS, a0, t0
restore_sc_msareg 29, SC32_MSAREGS, a0, t0
restore_sc_msareg 30, SC32_MSAREGS, a0, t0
restore_sc_msareg 31, SC32_MSAREGS, a0, t0
jr ra
li v0, 0
END(_restore_msa_context32)

#endif /* CONFIG_MIPS32_COMPAT */

#endif /* CONFIG_CPU_HAS_MSA */

.set reorder

.type fault@function
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