Skip to content

Commit

Permalink
Make ARMAsmPrinter generate the correct alignment specifier syntax in…
Browse files Browse the repository at this point in the history 
… instructions.

The Printer will now print instructions with the correct alignment specifier syntax, like
    vld1.8  {d16}, [r0:64]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
  • Loading branch information
@kbeyls
kbeyls committed Feb 22, 2013
1 parent 351b7a1 commit 29e05fe
Show file tree
Hide file tree
Showing 28 changed files with 408 additions and 409 deletions.
3 changes: 1 addition & 2 deletions lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -627,8 +627,7 @@ void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
O << markup("<mem:") << "[";
printRegName(O, MO1.getReg());
if (MO2.getImm()) {
// FIXME: Both darwin as and GNU as violate ARM docs here.
O << ", :" << (MO2.getImm() << 3);
O << ":" << (MO2.getImm() << 3);
}
O << "]" << markup(">");
}
Expand Down
4 changes: 2 additions & 2 deletions test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ define void @test_sqrt(<4 x float>* %X) nounwind {

; CHECK: movw r1, :lower16:{{.*}}
; CHECK: movt r1, :upper16:{{.*}}
; CHECK: vld1.64 {{.*}}, [r1, :128]
; CHECK: vld1.64 {{.*}}, [r1:128]
; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}}
; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}}
; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}}
Expand Down Expand Up @@ -252,7 +252,7 @@ define void @test_powi(<4 x float>* %X) nounwind {

; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
; CHECK: movt [[reg0]], :upper16:{{.*}}
; CHECK: vld1.64 {{.*}}, :128
; CHECK: vld1.64 {{.*}}:128
; CHECK: vmul.f32 {{.*}}

; CHECK: vst1.64
Expand Down
12 changes: 6 additions & 6 deletions test/CodeGen/ARM/2012-08-09-neon-extload.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ define void @test_v2i8tov2i32() {

%i32val = sext <2 x i8> %i8val to <2 x i32>
store <2 x i32> %i32val, <2 x i32>* @var_v2i32
; CHECK: vld1.16 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :16]
; CHECK: vld1.16 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:16]
; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}}

Expand All @@ -32,7 +32,7 @@ define void @test_v2i8tov2i64() {

%i64val = sext <2 x i8> %i8val to <2 x i64>
store <2 x i64> %i64val, <2 x i64>* @var_v2i64
; CHECK: vld1.16 {d{{[0-9]+}}[0]}, [{{r[0-9]+}}, :16]
; CHECK: vld1.16 {d{{[0-9]+}}[0]}, [{{r[0-9]+}}:16]
; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}}
; CHECK: vmovl.s32 {{q[0-9]+}}, {{d[0-9]+}}
Expand All @@ -50,7 +50,7 @@ define void @test_v4i8tov4i16() {

%i16val = sext <4 x i8> %i8val to <4 x i16>
store <4 x i16> %i16val, <4 x i16>* @var_v4i16
; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :32]
; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
; CHECK-NOT: vmovl.s16

Expand All @@ -65,7 +65,7 @@ define void @test_v4i8tov4i32() {

%i16val = sext <4 x i8> %i8val to <4 x i32>
store <4 x i32> %i16val, <4 x i32>* @var_v4i32
; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :32]
; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}}

Expand All @@ -79,7 +79,7 @@ define void @test_v2i16tov2i32() {

%i32val = sext <2 x i16> %i16val to <2 x i32>
store <2 x i32> %i32val, <2 x i32>* @var_v2i32
; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :32]
; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]]
; CHECK-NOT: vmovl

Expand All @@ -94,7 +94,7 @@ define void @test_v2i16tov2i64() {

%i64val = sext <2 x i16> %i16val to <2 x i64>
store <2 x i64> %i64val, <2 x i64>* @var_v2i64
; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :32]
; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]]
; CHECK: vmovl.s32 {{q[0-9]+}}, d[[LOAD]]

Expand Down
10 changes: 5 additions & 5 deletions test/CodeGen/ARM/neon_ld2.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,10 +7,10 @@
; CHECK: vadd.i64 q
; CHECK: vst1.64
; SWIFT: t1
; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}}
; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}}
; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
; SWIFT: vadd.i64 q
; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}}
; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
define void @t1(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind {
entry:
%0 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1]
Expand All @@ -28,8 +28,8 @@ entry:
; CHECK: vmov r0, r1, d
; CHECK: vmov r2, r3, d
; SWIFT: t2
; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}}
; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}}
; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
; SWIFT: vsub.i64 q
; SWIFT: vmov r0, r1, d
; SWIFT: vmov r2, r3, d
Expand Down
4 changes: 2 additions & 2 deletions test/CodeGen/ARM/reg_sequence.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -242,8 +242,8 @@ define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind {
; CHECK: vldr
; CHECK-NOT: vmov d{{.*}}, d16
; CHECK: vmov.i32 d17
; CHECK-NEXT: vst1.64 {d16, d17}, [r0, :128]
; CHECK-NEXT: vst1.64 {d16, d17}, [r0, :128]
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
%3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2]
%4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
store <4 x float> %4, <4 x float>* undef, align 16
Expand Down
4 changes: 2 additions & 2 deletions test/CodeGen/ARM/spill-q.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,8 +12,8 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
define void @aaa(%quuz* %this, i8* %block) {
; CHECK: aaa:
; CHECK: bic {{.*}}, #15
; CHECK: vst1.64 {{.*}}sp, :128
; CHECK: vld1.64 {{.*}}sp, :128
; CHECK: vst1.64 {{.*}}sp:128
; CHECK: vld1.64 {{.*}}sp:128
entry:
%aligned_vec = alloca <4 x float>, align 16
%"alloca point" = bitcast i32 0 to i32
Expand Down
8 changes: 4 additions & 4 deletions test/CodeGen/ARM/vld1.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
define <8 x i8> @vld1i8(i8* %A) nounwind {
;CHECK: vld1i8:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld1.8 {d16}, [r0, :64]
;CHECK: vld1.8 {d16}, [r0:64]
%tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 16)
ret <8 x i8> %tmp1
}
Expand Down Expand Up @@ -68,15 +68,15 @@ define <1 x i64> @vld1i64(i64* %A) nounwind {
define <16 x i8> @vld1Qi8(i8* %A) nounwind {
;CHECK: vld1Qi8:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld1.8 {d16, d17}, [r0, :64]
;CHECK: vld1.8 {d16, d17}, [r0:64]
%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
ret <16 x i8> %tmp1
}

;Check for a post-increment updating load.
define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind {
;CHECK: vld1Qi8_update:
;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}, :64]!
;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}:64]!
%A = load i8** %ptr
%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
%tmp2 = getelementptr i8* %A, i32 16
Expand All @@ -87,7 +87,7 @@ define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind {
define <8 x i16> @vld1Qi16(i16* %A) nounwind {
;CHECK: vld1Qi16:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld1.16 {d16, d17}, [r0, :128]
;CHECK: vld1.16 {d16, d17}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
%tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %tmp0, i32 32)
ret <8 x i16> %tmp1
Expand Down
14 changes: 7 additions & 7 deletions test/CodeGen/ARM/vld2.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@
define <8 x i8> @vld2i8(i8* %A) nounwind {
;CHECK: vld2i8:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld2.8 {d16, d17}, [r0, :64]
;CHECK: vld2.8 {d16, d17}, [r0:64]
%tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8* %A, i32 8)
%tmp2 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 1
Expand All @@ -25,7 +25,7 @@ define <8 x i8> @vld2i8(i8* %A) nounwind {
define <4 x i16> @vld2i16(i16* %A) nounwind {
;CHECK: vld2i16:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld2.16 {d16, d17}, [r0, :128]
;CHECK: vld2.16 {d16, d17}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
%tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i8* %tmp0, i32 32)
%tmp2 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 0
Expand Down Expand Up @@ -74,7 +74,7 @@ define <2 x float> @vld2f_update(float** %ptr) nounwind {
define <1 x i64> @vld2i64(i64* %A) nounwind {
;CHECK: vld2i64:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld1.64 {d16, d17}, [r0, :128]
;CHECK: vld1.64 {d16, d17}, [r0:128]
%tmp0 = bitcast i64* %A to i8*
%tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i8* %tmp0, i32 32)
%tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0
Expand All @@ -86,7 +86,7 @@ define <1 x i64> @vld2i64(i64* %A) nounwind {
define <16 x i8> @vld2Qi8(i8* %A) nounwind {
;CHECK: vld2Qi8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64]
;CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64]
%tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 8)
%tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
Expand All @@ -97,7 +97,7 @@ define <16 x i8> @vld2Qi8(i8* %A) nounwind {
;Check for a post-increment updating load with register increment.
define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind {
;CHECK: vld2Qi8_update:
;CHECK: vld2.8 {d16, d17, d18, d19}, [r2, :128], r1
;CHECK: vld2.8 {d16, d17, d18, d19}, [r2:128], r1
%A = load i8** %ptr
%tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 16)
%tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
Expand All @@ -111,7 +111,7 @@ define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind {
define <8 x i16> @vld2Qi16(i16* %A) nounwind {
;CHECK: vld2Qi16:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128]
;CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
%tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i8* %tmp0, i32 16)
%tmp2 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 0
Expand All @@ -123,7 +123,7 @@ define <8 x i16> @vld2Qi16(i16* %A) nounwind {
define <4 x i32> @vld2Qi32(i32* %A) nounwind {
;CHECK: vld2Qi32:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256]
;CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256]
%tmp0 = bitcast i32* %A to i8*
%tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp0, i32 64)
%tmp2 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 0
Expand Down
8 changes: 4 additions & 4 deletions test/CodeGen/ARM/vld3.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@
define <8 x i8> @vld3i8(i8* %A) nounwind {
;CHECK: vld3i8:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld3.8 {d16, d17, d18}, [r0, :64]
;CHECK: vld3.8 {d16, d17, d18}, [r0:64]
%tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 32)
%tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2
Expand Down Expand Up @@ -74,7 +74,7 @@ define <2 x float> @vld3f(float* %A) nounwind {
define <1 x i64> @vld3i64(i64* %A) nounwind {
;CHECK: vld3i64:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld1.64 {d16, d17, d18}, [r0, :64]
;CHECK: vld1.64 {d16, d17, d18}, [r0:64]
%tmp0 = bitcast i64* %A to i8*
%tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8* %tmp0, i32 16)
%tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0
Expand All @@ -86,8 +86,8 @@ define <1 x i64> @vld3i64(i64* %A) nounwind {
define <16 x i8> @vld3Qi8(i8* %A) nounwind {
;CHECK: vld3Qi8:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld3.8 {d16, d18, d20}, [r0, :64]!
;CHECK: vld3.8 {d17, d19, d21}, [r0, :64]
;CHECK: vld3.8 {d16, d18, d20}, [r0:64]!
;CHECK: vld3.8 {d17, d19, d21}, [r0:64]
%tmp1 = call %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8* %A, i32 32)
%tmp2 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 2
Expand Down
18 changes: 9 additions & 9 deletions test/CodeGen/ARM/vld4.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@
define <8 x i8> @vld4i8(i8* %A) nounwind {
;CHECK: vld4i8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64]
;CHECK: vld4.8 {d16, d17, d18, d19}, [r0:64]
%tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 8)
%tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2
Expand All @@ -25,7 +25,7 @@ define <8 x i8> @vld4i8(i8* %A) nounwind {
;Check for a post-increment updating load with register increment.
define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind {
;CHECK: vld4i8_update:
;CHECK: vld4.8 {d16, d17, d18, d19}, [r2, :128], r1
;CHECK: vld4.8 {d16, d17, d18, d19}, [r2:128], r1
%A = load i8** %ptr
%tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 16)
%tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
Expand All @@ -39,7 +39,7 @@ define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind {
define <4 x i16> @vld4i16(i16* %A) nounwind {
;CHECK: vld4i16:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128]
;CHECK: vld4.16 {d16, d17, d18, d19}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
%tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8* %tmp0, i32 16)
%tmp2 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 0
Expand All @@ -51,7 +51,7 @@ define <4 x i16> @vld4i16(i16* %A) nounwind {
define <2 x i32> @vld4i32(i32* %A) nounwind {
;CHECK: vld4i32:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256]
;CHECK: vld4.32 {d16, d17, d18, d19}, [r0:256]
%tmp0 = bitcast i32* %A to i8*
%tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8* %tmp0, i32 32)
%tmp2 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 0
Expand All @@ -74,7 +74,7 @@ define <2 x float> @vld4f(float* %A) nounwind {
define <1 x i64> @vld4i64(i64* %A) nounwind {
;CHECK: vld4i64:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld1.64 {d16, d17, d18, d19}, [r0, :256]
;CHECK: vld1.64 {d16, d17, d18, d19}, [r0:256]
%tmp0 = bitcast i64* %A to i8*
%tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8* %tmp0, i32 64)
%tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0
Expand All @@ -86,8 +86,8 @@ define <1 x i64> @vld4i64(i64* %A) nounwind {
define <16 x i8> @vld4Qi8(i8* %A) nounwind {
;CHECK: vld4Qi8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]!
;CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]
;CHECK: vld4.8 {d16, d18, d20, d22}, [r0:256]!
;CHECK: vld4.8 {d17, d19, d21, d23}, [r0:256]
%tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8* %A, i32 64)
%tmp2 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 2
Expand All @@ -111,8 +111,8 @@ define <8 x i16> @vld4Qi16(i16* %A) nounwind {
;Check for a post-increment updating load.
define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind {
;CHECK: vld4Qi16_update:
;CHECK: vld4.16 {d16, d18, d20, d22}, [r1, :64]!
;CHECK: vld4.16 {d17, d19, d21, d23}, [r1, :64]!
;CHECK: vld4.16 {d16, d18, d20, d22}, [r1:64]!
;CHECK: vld4.16 {d17, d19, d21, d23}, [r1:64]!
%A = load i16** %ptr
%tmp0 = bitcast i16* %A to i8*
%tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 8)
Expand Down
12 changes: 6 additions & 6 deletions test/CodeGen/ARM/vlddup.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ define <8 x i8> @vld1dupi8(i8* %A) nounwind {
define <4 x i16> @vld1dupi16(i16* %A) nounwind {
;CHECK: vld1dupi16:
;Check the alignment value. Max for this instruction is 16 bits:
;CHECK: vld1.16 {d16[]}, [r0, :16]
;CHECK: vld1.16 {d16[]}, [r0:16]
%tmp1 = load i16* %A, align 8
%tmp2 = insertelement <4 x i16> undef, i16 %tmp1, i32 0
%tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> undef, <4 x i32> zeroinitializer
Expand All @@ -23,7 +23,7 @@ define <4 x i16> @vld1dupi16(i16* %A) nounwind {
define <2 x i32> @vld1dupi32(i32* %A) nounwind {
;CHECK: vld1dupi32:
;Check the alignment value. Max for this instruction is 32 bits:
;CHECK: vld1.32 {d16[]}, [r0, :32]
;CHECK: vld1.32 {d16[]}, [r0:32]
%tmp1 = load i32* %A, align 8
%tmp2 = insertelement <2 x i32> undef, i32 %tmp1, i32 0
%tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> undef, <2 x i32> zeroinitializer
Expand All @@ -32,7 +32,7 @@ define <2 x i32> @vld1dupi32(i32* %A) nounwind {

define <2 x float> @vld1dupf(float* %A) nounwind {
;CHECK: vld1dupf:
;CHECK: vld1.32 {d16[]}, [r0, :32]
;CHECK: vld1.32 {d16[]}, [r0:32]
%tmp0 = load float* %A
%tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
Expand All @@ -51,7 +51,7 @@ define <16 x i8> @vld1dupQi8(i8* %A) nounwind {

define <4 x float> @vld1dupQf(float* %A) nounwind {
;CHECK: vld1dupQf:
;CHECK: vld1.32 {d16[], d17[]}, [r0, :32]
;CHECK: vld1.32 {d16[], d17[]}, [r0:32]
%tmp0 = load float* %A
%tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
Expand Down Expand Up @@ -109,7 +109,7 @@ define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind {
define <2 x i32> @vld2dupi32(i8* %A) nounwind {
;CHECK: vld2dupi32:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld2.32 {d16[], d17[]}, [r0, :64]
;CHECK: vld2.32 {d16[], d17[]}, [r0:64]
%tmp0 = tail call %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %A, <2 x i32> undef, <2 x i32> undef, i32 0, i32 16)
%tmp1 = extractvalue %struct.__neon_int2x32x2_t %tmp0, 0
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
Expand Down Expand Up @@ -194,7 +194,7 @@ define <2 x i32> @vld4dupi32(i8* %A) nounwind {
;CHECK: vld4dupi32:
;Check the alignment value. An 8-byte alignment is allowed here even though
;it is smaller than the total size of the memory being loaded.
;CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r0, :64]
;CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r0:64]
%tmp0 = tail call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8* %A, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, i32 0, i32 8)
%tmp1 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 0
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
Expand Down
Loading

0 comments on commit 29e05fe

Please sign in to comment.