Verify regunit intervals along with virtreg intervals.

Don't cause regunit intervals to be computed just to verify them. Only
check the already cached intervals.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161183 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/MachineVerifier.cpp

@@ -1170,6 +1170,11 @@ void MachineVerifier::verifyLiveIntervals() {
     assert(Reg == LI.reg && "Invalid reg to interval mapping");
     verifyLiveInterval(LI);
   }
+
+  // Verify all the cached regunit intervals.
+  for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
+    if (const LiveInterval *LI = LiveInts->getCachedRegUnit(i))
+      verifyLiveInterval(*LI);
 }
 
 void MachineVerifier::verifyLiveIntervalValue(const LiveInterval &LI,
@@ -1227,7 +1232,7 @@ void MachineVerifier::verifyLiveIntervalValue(const LiveInterval &LI,
         continue;
     } else {
       if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
-          !TRI->regsOverlap(LI.reg, MOI->getReg()))
+          !TRI->hasRegUnit(MOI->getReg(), LI.reg))
         continue;
     }
     hasDef = true;
@@ -1294,6 +1299,11 @@ MachineVerifier::verifyLiveIntervalSegment(const LiveInterval &LI,
   if (I->end == LiveInts->getMBBEndIdx(EndMBB))
     return;
 
+  // RegUnit intervals are allowed dead phis.
+  if (!TargetRegisterInfo::isVirtualRegister(LI.reg) && VNI->isPHIDef() &&
+      I->start == VNI->def && I->end == VNI->def.getDeadSlot())
+    return;
+
   // The live segment is ending inside EndMBB
   const MachineInstr *MI =
     LiveInts->getInstructionFromIndex(I->end.getPrevSlot());
@@ -1371,7 +1381,7 @@ MachineVerifier::verifyLiveIntervalSegment(const LiveInterval &LI,
   for (;;) {
     assert(LiveInts->isLiveInToMBB(LI, MFI));
     // We don't know how to track physregs into a landing pad.
-    if (TargetRegisterInfo::isPhysicalRegister(LI.reg) &&
+    if (!TargetRegisterInfo::isVirtualRegister(LI.reg) &&
         MFI->isLandingPad()) {
       if (&*MFI == EndMBB)
         break;