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[X86] Remove two feature flags that covered sets of instructions that…
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… have no patterns or intrinsics. Since we don't check feature flags in the assembler parser for any instruction sets, these flags don't provide any value. This frees up 2 of the fully utilized feature flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228282 91177308-0d34-0410-b5e6-96231b3b80d8
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topperc committed Feb 5, 2015
1 parent 81eb6ca commit b8fa51d
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Showing 6 changed files with 4 additions and 21 deletions.
7 changes: 1 addition & 6 deletions lib/Target/X86/X86.td
Original file line number Diff line number Diff line change
Expand Up @@ -164,14 +164,10 @@ def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
"Enable SHA instructions",
[FeatureSSE2]>;
def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
"Support SGX instructions">;
def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
"Support PRFCHW instructions">;
def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
"Support RDSEED instruction">;
def FeatureSMAP : SubtargetFeature<"smap", "HasSMAP", "true",
"Support SMAP instructions">;
def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
"Use LEA for adjusting the stack pointer">;
def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
Expand Down Expand Up @@ -372,7 +368,6 @@ class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
FeatureHLE,
FeatureADX,
FeatureRDSEED,
FeatureSMAP,
FeatureSlowIncDec
]>;
def : BroadwellProc<"broadwell">;
Expand All @@ -395,7 +390,7 @@ class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel,
FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
FeatureSlowIncDec, FeatureSGX]>;
FeatureSlowIncDec]>;
def : SkylakeProc<"skylake">;
def : SkylakeProc<"skx">; // Legacy alias.

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2 changes: 0 additions & 2 deletions lib/Target/X86/X86InstrInfo.td
Original file line number Diff line number Diff line change
Expand Up @@ -774,10 +774,8 @@ def HasHLE : Predicate<"Subtarget->hasHLE()">;
def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
def HasADX : Predicate<"Subtarget->hasADX()">;
def HasSHA : Predicate<"Subtarget->hasSHA()">;
def HasSGX : Predicate<"Subtarget->hasSGX()">;
def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
def HasSMAP : Predicate<"Subtarget->hasSMAP()">;
def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
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4 changes: 2 additions & 2 deletions lib/Target/X86/X86InstrSGX.td
Original file line number Diff line number Diff line change
Expand Up @@ -17,8 +17,8 @@

// ENCLS - Execute an Enclave System Function of Specified Leaf Number
def ENCLS : I<0x01, MRM_CF, (outs), (ins),
"encls", []>, TB, Requires<[HasSGX]>;
"encls", []>, TB;

// ENCLU - Execute an Enclave User Function of Specified Leaf Number
def ENCLU : I<0x01, MRM_D7, (outs), (ins),
"enclu", []>, TB, Requires<[HasSGX]>;
"enclu", []>, TB;
2 changes: 1 addition & 1 deletion lib/Target/X86/X86InstrSystem.td
Original file line number Diff line number Diff line change
Expand Up @@ -560,7 +560,7 @@ def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),

//===----------------------------------------------------------------------===//
// SMAP Instruction
let Predicates = [HasSMAP], Defs = [EFLAGS] in {
let Defs = [EFLAGS] in {
def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
}
2 changes: 0 additions & 2 deletions lib/Target/X86/X86Subtarget.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -257,10 +257,8 @@ void X86Subtarget::initializeEnvironment() {
HasVLX = false;
HasADX = false;
HasSHA = false;
HasSGX = false;
HasPRFCHW = false;
HasRDSEED = false;
HasSMAP = false;
IsBTMemSlow = false;
IsSHLDSlow = false;
IsUAMemFast = false;
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8 changes: 0 additions & 8 deletions lib/Target/X86/X86Subtarget.h
Original file line number Diff line number Diff line change
Expand Up @@ -134,18 +134,12 @@ class X86Subtarget final : public X86GenSubtargetInfo {
/// Processor has SHA instructions.
bool HasSHA;

/// Processor has SGX instructions.
bool HasSGX;

/// Processor has PRFCHW instructions.
bool HasPRFCHW;

/// Processor has RDSEED instructions.
bool HasRDSEED;

/// Processor has SMAP instructions.
bool HasSMAP;

/// True if BT (bit test) of memory instructions are slow.
bool IsBTMemSlow;

Expand Down Expand Up @@ -364,10 +358,8 @@ class X86Subtarget final : public X86GenSubtargetInfo {
bool hasHLE() const { return HasHLE; }
bool hasADX() const { return HasADX; }
bool hasSHA() const { return HasSHA; }
bool hasSGX() const { return HasSGX; }
bool hasPRFCHW() const { return HasPRFCHW; }
bool hasRDSEED() const { return HasRDSEED; }
bool hasSMAP() const { return HasSMAP; }
bool isBTMemSlow() const { return IsBTMemSlow; }
bool isSHLDSlow() const { return IsSHLDSlow; }
bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
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