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@CPUNexus

CPUNexus

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  1. VeriGPU VeriGPU Public

    Forked from hughperkins/VeriGPU

    OpenSource GPU, in Verilog, loosely based on RISC-V ISA

    SystemVerilog 1

  2. vortex vortex Public

    Forked from vortexgpgpu/vortex

    Verilog 1

  3. tiny-gpu tiny-gpu Public

    Forked from adam-maj/tiny-gpu

    A minimal GPU design in Verilog to learn how GPUs work from the ground up

    SystemVerilog 1

  4. ccpu ccpu Public

    Forked from imihajlow/ccpu

    A 8-bit computer made of 74xx series logic gates and memory ICs.

    Assembly

  5. PASC PASC Public

    Forked from jbush001/PASC

    Parallel Array of Simple Cores. Multicore processor.

    Verilog

  6. RISC-Processor RISC-Processor Public

    Forked from jbush001/RISC-Processor

    32-bit RISC processor

    Verilog

Repositories

Showing 10 of 32 repositories
  • CPUNexus/Tridora-CPU-mirror’s past year of commit activity
    Pascal 0 1 0 0 Updated Oct 24, 2024
  • darkriscv Public Forked from darklife/darkriscv

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

    CPUNexus/darkriscv’s past year of commit activity
    Verilog 0 BSD-3-Clause 297 0 0 Updated Oct 24, 2024
  • zipcpu Public Forked from ZipCPU/zipcpu

    A small, light weight, RISC CPU soft core

    CPUNexus/zipcpu’s past year of commit activity
    Verilog 0 165 0 0 Updated Oct 24, 2024
  • vortex Public Forked from vortexgpgpu/vortex
    CPUNexus/vortex’s past year of commit activity
    Verilog 1 Apache-2.0 293 0 0 Updated Oct 24, 2024
  • tiny-gpu Public Forked from adam-maj/tiny-gpu

    A minimal GPU design in Verilog to learn how GPUs work from the ground up

    CPUNexus/tiny-gpu’s past year of commit activity
    SystemVerilog 1 611 0 0 Updated Aug 18, 2024
  • microwatt Public Forked from antonblanchard/microwatt

    A tiny Open POWER ISA softcore written in VHDL 2008

    CPUNexus/microwatt’s past year of commit activity
    Verilog 0 102 0 0 Updated Aug 17, 2024
  • openc910 Public Forked from XUANTIE-RV/openc910

    OpenXuantie - OpenC910 Core

    CPUNexus/openc910’s past year of commit activity
    Verilog 0 Apache-2.0 323 0 0 Updated Jun 28, 2024
  • cva6 Public Forked from openhwgroup/cva6

    The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

    CPUNexus/cva6’s past year of commit activity
    Assembly 0 728 0 0 Updated Jun 26, 2024
  • neorv32-verilog Public template Forked from stnolting/neorv32-verilog

    ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

    CPUNexus/neorv32-verilog’s past year of commit activity
    Verilog 0 BSD-3-Clause 17 0 0 Updated Jun 24, 2024
  • neorv32 Public Forked from stnolting/neorv32

    🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

    CPUNexus/neorv32’s past year of commit activity
    VHDL 0 BSD-3-Clause 246 0 0 Updated Jun 23, 2024

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