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Chris-Du · May 2, 2023 · c367702 · c367702
1 parent 7137b43
commit c367702
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Showing 4 changed files with 91 additions and 17 deletions.
diff --git a/arbiter_2to1_gate.sv b/arbiter_2to1_gate.sv
@@ -1,6 +1,5 @@
 `timescale 1ns/1ps
 
-import SystemVerilogCSP::*;
 parameter WIDTH_packet = 57;
 module arbiter_2to1_gate (
     input logic in1_req,
@@ -15,13 +14,17 @@ module arbiter_2to1_gate (
 );
 
     parameter FL = 2, BL = 1;
+    parameter WIDTH_packet = 57;
     logic [WIDTH_packet-1:0] in_packet;
     logic prio;
     initial begin
         prio = 0;
     end
 
     always begin
+        in1_ack = 0;
+        in2_ack = 0;
+        wait(in1_req || in2_req);
         if(in1_req && in2_req) begin
             // contention
             if(prio) begin
@@ -30,7 +33,6 @@ module arbiter_2to1_gate (
                 in_packet = in2_data;
                 in2_ack = 1;
                 wait(in2_req == 0);
-                in2_ack = 0;
                 #FL;
                 out_data = in_packet;
                 out_req = 1;
@@ -45,7 +47,6 @@ module arbiter_2to1_gate (
                 in_packet = in1_data;
                 in1_ack = 1;
                 wait(in1_req == 0);
-                in1_ack = 0;
                 #FL;
                 out_data = in_packet;
                 out_req = 1;
@@ -60,7 +61,6 @@ module arbiter_2to1_gate (
             in_packet = in1_data;
             in1_ack = 1;
             wait(in1_req == 0);
-            in1_ack = 0;
             #FL;
             out_data = in_packet;
             out_req = 1;
@@ -73,7 +73,6 @@ module arbiter_2to1_gate (
             in_packet = in2_data;
             in2_ack = 1;
             wait(in2_req == 0);
-            in2_ack = 0;
             #FL;
             out_data = in_packet;
             out_req = 1;

diff --git a/arbiter_2to1_gate_tb.sv b/arbiter_2to1_gate_tb.sv
@@ -0,0 +1,78 @@
+`timescale 1ns/1ps
+
+module arbiter_2to1_gate_tb (
+);
+    parameter WIDTH_packet = 57;
+    parameter FL = 2, BL = 1;
+    logic in1_req,in1_ack;
+    logic [WIDTH_packet-1:0] in1_data;
+    logic in2_req;
+    logic in2_ack;
+    logic [WIDTH_packet-1:0] in2_data;
+    logic out_req;
+    logic out_ack;
+    logic [WIDTH_packet-1:0] out_data;
+
+    arbiter_2to1_gate DUT(
+         in1_req,in1_ack,in1_data,in2_req,in2_ack,in2_data,out_req,out_ack,out_data
+    );
+
+    logic [WIDTH_packet-1:0] out_data_print;
+    integer count;
+
+    always begin
+        #FL;
+        /*
+        if(i%1 == 0) begin
+            in[0].Send(count);
+            count = count + 1;
+        end
+        if(i%2 == 1) begin
+            in[1].Send(count);
+            count = count + 1;
+        end
+        */
+        fork
+            begin
+                in1_data = count;
+                in1_req = 1;
+                wait(in1_ack == 1);
+                in1_req = 0;
+            end
+            begin
+                in2_data = count + 1;
+                in2_req = 1;
+                wait(in2_ack == 1);
+                in2_req = 0;
+            end
+            /*
+            in[0].Send(count);
+            in[1].Send(count+1);
+            */
+        join
+
+        count = count + 2;
+    end
+
+    always begin
+        wait(out_req == 1);
+        out_data_print = out_data;
+        out_ack = 1;
+        wait(out_req == 0);
+        out_ack = 0;
+        $display("out data: %d",out_data_print);
+        #BL;
+    end
+
+    initial begin
+        count = 0;
+        in1_req = 0;
+        in2_req = 0;
+        out_ack = 0;
+
+
+        #100;
+        $stop();
+    end
+
+endmodule
diff --git a/output_ctrl_gate.sv b/output_ctrl_gate.sv
@@ -1,6 +1,5 @@
-`timescale 1ns/1ps
+`timescale 1ns/1ns
 
-import SystemVerilogCSP::*;
 module output_ctrl_gate (
     interface in1, in2, in3, in4, out
 );
@@ -10,21 +9,19 @@ module output_ctrl_gate (
     logic out1_req,out2_req,out3_req;
     logic out1_ack,out2_ack,out3_ack;
     logic [WIDTH_packet-1:0] out1_data, out2_data,out3_data, interface_out_data;
-    
-    arbiter_2to1 arb1(in1.req, in1.ack,in1.data,in2.req,in2.ack,in2.data,out1_req,out1_ack,out1_data);
-    arbiter_2to1 arb2(in3.req, in3.ack,in3.data,in4.req,in4.ack,in4.data,out2_req,out2_ack,out2_data);
-    arbiter_2to1 final_out(out1_req,out1_ack,out1_data,out2_req,out2_ack,out2_data, out3_req,out3_ack,out3_data);
+
+    arbiter_2to1_gate arb1(in1.req, in1.ack,in1.data,in2.req,in2.ack,in2.data,out1_req,out1_ack,out1_data);
+    arbiter_2to1_gate arb2(in3.req, in3.ack,in3.data,in4.req,in4.ack,in4.data,out2_req,out2_ack,out2_data);
+    arbiter_2to1_gate final_out(out1_req,out1_ack,out1_data,out2_req,out2_ack,out2_data, out3_req,out3_ack,out3_data);
 
     always begin
         out3_ack = 0;
         wait(out3_req);
-        interface_out_data = out3_data;
         #FL;
         out3_ack = 1;
-        out.Send(interface_out_data);
-        wait(!out3_req)
+        out.Send(out3_data);
+        wait(!out3_req);
         #BL;
     end
 
-
 endmodule
diff --git a/output_ctrl_tb.sv b/output_ctrl_tb.sv
@@ -1,4 +1,4 @@
-`timescale 1ns/1ps
+`timescale 1ns/1ns
 
 import SystemVerilogCSP::*;
 
@@ -9,7 +9,7 @@ module output_ctrl_tb;
     Channel #(.hsProtocol(P4PhaseBD), .WIDTH(WIDTH_packet)) out();
     logic [WIDTH_packet-1:0] out_data;
     integer single,double,triple,quad,count;
-    output_ctrl dut(
+    output_ctrl_gate dut(
         in[0],
         in[1],
         in[2],