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Commits on Dec 3, 2018

• [RISCV] Fix test/MC/Disassembler/RISCV/invalid-instruction.txt after rL347988

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Commits on Dec 1, 2018

• [RISCV] Remove RV64I SLLW/SRLW/SRAW patterns and add new test cases

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Commits on Nov 30, 2018

• [RISCV] Add additional CSR instruction aliases (imm. operands)

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• [RISCV] Add UNIMP instruction (32- and 16-bit forms)

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• [SelectionDAG] Support result type promotion for FLT_ROUNDS_

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• [SelectionDAG] Support promotion of PREFETCH operands

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• [SelectionDAG] Support promotion of FRAMEADDR/RETURNADDR operands

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• [TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement for RISC-V

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• [RISCV] Introduce codegen patterns for instructions introduced in RV64I

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• [docs][AtomicExpandPass] Document the alternate lowering strategy for part-word atomicrmw/cmpxchg

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Commits on Nov 29, 2018

• [RISCV] Implement codegen for cmpxchg on RV32IA

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Commits on Nov 28, 2018

• [RISCV] Support .option push and .option pop

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Commits on Nov 16, 2018

• [RISCV][NFC] Define and use the new CA instruction format

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• [RISCV] Constant materialisation for RV64I

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Commits on Nov 15, 2018

• [RISCV] Mark C.EBREAK instruction as having side effects

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• [RISCV] Mark FREM as Expand

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• [RISCV] Introduce the RISCVMatInt::generateInstSeq helper

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Commits on Nov 12, 2018

• [RISCV] Support .option relax and .option norelax

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Commits on Nov 9, 2018

• [RISCV] Avoid unnecessary XOR for seteq/setne 0

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• [RISCV] Update test/CodeGen/RISCV/calling-conv.ll after rL346432

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Commits on Nov 2, 2018

• [RISCV] Add some missing expansions for floating-point intrinsics

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Commits on Oct 25, 2018

• [RISCV] Use PatFrags for variable shift patterns

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Commits on Oct 12, 2018

• [RISCV] Eliminate unnecessary masking of promoted shift amounts

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Commits on Oct 11, 2018

• [RISCV] Re-generate test/CodeGen/RISCV/vararg.ll after r344142

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Commits on Oct 8, 2018

• [RISCV] Update alu8.ll and alu16.ll test cases

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• [SelectionDAGBuilder][NFC] Pass LHSTy to getShiftAmountTy rather than RHSTy

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Commits on Oct 7, 2018

• [RISCV] Introduce alu8.ll and alu16.ll tests

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Commits on Oct 6, 2018

• [RISCV] Compress addiw rd, x0, simm6 to c.li rd, simm6

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Commits on Oct 5, 2018

• [RISCV] Regenerate several tests now enableMultipleCopyHints is enabled by default

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Commits on Oct 4, 2018

• [RISCV] Remove overzealous is64Bit checks

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• [RISCV][NFC] Remove dead CHECK lines from vararg.ll test

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• [RISCV] Bugfix for floats passed on the stack with the ILP32 ABI on RV32F

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• [RISCV][NFC] Fix naming of RISCVISelLowering::{LowerRETURNADDR,LowerFRAMEADDR}

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Commits on Oct 3, 2018

• [RISCV] Handle redundant SplitF64+BuildPairF64 pairs in a DAGCombine

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• [RISCV][NFC] Refactor LocVT<->ValVT converstion in RISCVISelLowering

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