added files from pull requests (de4-230 and labfor.ru support)

board/de4_230/DE4_230.qpf

@@ -0,0 +1,32 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2016  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Intel and sold by Intel or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.1.0 Build 196 10/24/2016 SJ Standard Edition
+# Date created = 14:39:37  November 29, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "16.1"
+DATE = "14:39:37  November 29, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "DE4_230"
+PROJECT_REVISION = "DE4_GOLDEN_TOP"

board/de4_230/DE4_230.sdc

@@ -0,0 +1,83 @@
+#**************************************************************
+# This .sbc file is created by Terasic Tool.
+# Users are recommended to modify this file to match users logic.
+#**************************************************************
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Load
+#**************************************************************
+
+
+