Most boards: Update URLs to point to digilent.com/reference and resou…

…rce centers
Digilent · Mar 3, 2022 · bc3730c · bc3730c
1 parent f97e0d9
commit bc3730c
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Showing 22 changed files with 45 additions and 45 deletions.
diff --git a/new/board_files/arty-a7-100/E.0/1.1/board.xml b/new/board_files/arty-a7-100/E.0/1.1/board.xml
@@ -22,14 +22,14 @@ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 SOFTWARE.
 -->
-<board schema_version="2.0" vendor="digilentinc.com" name="arty-a7-100" display_name="Arty A7-100" url="https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start" preset_file="preset.xml" >
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-a7-100" display_name="Arty A7-100" url="https://digilent.com/reference/programmable-logic/arty-a7/start" preset_file="preset.xml" >
 <compatible_board_revisions>
   <revision id="0">E.0</revision>
 </compatible_board_revisions>
 <file_version>1.1</file_version>
 <description>Arty A7-100</description>
 <components>
-  <component name="part0" display_name="Arty A7-100" type="fpga" part_name="xc7a100tcsg324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start">
+  <component name="part0" display_name="Arty A7-100" type="fpga" part_name="xc7a100tcsg324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/arty-a7/start">
     <interfaces>
       <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
 		<description>DDR3 board interface, it can use MIG IP for connection.</description>

diff --git a/new/board_files/arty-a7-35/E.0/1.1/board.xml b/new/board_files/arty-a7-35/E.0/1.1/board.xml
@@ -22,14 +22,14 @@ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 SOFTWARE.
 -->
-<board schema_version="2.0" vendor="digilentinc.com" name="arty-a7-35" display_name="Arty A7-35" url="https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start" preset_file="preset.xml" >
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-a7-35" display_name="Arty A7-35" url="https://digilent.com/reference/programmable-logic/arty-a7/start" preset_file="preset.xml" >
 <compatible_board_revisions>
   <revision id="0">E.0</revision>
 </compatible_board_revisions>
 <file_version>1.1</file_version>
 <description>Arty A7-35</description>
 <components>
-  <component name="part0" display_name="Arty A7-35" type="fpga" part_name="xc7a35ticsg324-1L" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start"> <!--CONFIRM URL-->
+  <component name="part0" display_name="Arty A7-35" type="fpga" part_name="xc7a35ticsg324-1L" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/arty-a7/start"> <!--CONFIRM URL-->
     <interfaces>
       <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
 		<description>DDR3 board interface, it can use MIG IP for connection.</description>

diff --git a/new/board_files/arty-s7-25/E.0/board.xml b/new/board_files/arty-s7-25/E.0/board.xml
@@ -22,14 +22,14 @@ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 SOFTWARE.
 -->
-<board schema_version="2.0" vendor="digilentinc.com" name="arty-s7-25" display_name="Arty S7-25" url="https://reference.digilentinc.com/reference/programmable-logic/arty-s7/start" preset_file="preset.xml" >
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-s7-25" display_name="Arty S7-25" url="https://digilent.com/reference/programmable-logic/arty-s7/start" preset_file="preset.xml" >
 <compatible_board_revisions>
   <revision id="0">E.0</revision>
 </compatible_board_revisions>
-<file_version>1.0</file_version>
+<file_version>1.1</file_version>
 <description>Arty S7-25</description>
 <components>
-  <component name="part0" display_name="Arty S7-25" type="fpga" part_name="xc7s25csga324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/arty-s7/start">
+  <component name="part0" display_name="Arty S7-25" type="fpga" part_name="xc7s25csga324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/arty-s7/start">
     <interfaces>
       <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
 		<description>DDR3 board interface, it can use MIG IP for connection.</description>

diff --git a/new/board_files/arty-s7-50/B.0/board.xml b/new/board_files/arty-s7-50/B.0/board.xml
@@ -22,14 +22,14 @@ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 SOFTWARE.
 -->
-<board schema_version="2.0" vendor="digilentinc.com" name="arty-s7-50" display_name="Arty S7-50" url="https://reference.digilentinc.com/reference/programmable-logic/arty-s7/start" preset_file="preset.xml" >
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-s7-50" display_name="Arty S7-50" url="https://digilent.com/reference/programmable-logic/arty-s7/start" preset_file="preset.xml" >
 <compatible_board_revisions>
   <revision id="0">B.0</revision>
 </compatible_board_revisions>
-<file_version>1.0</file_version>
+<file_version>1.1</file_version>
 <description>Arty S7-50</description>
 <components>
-  <component name="part0" display_name="Arty S7-50" type="fpga" part_name="xc7s50csga324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/arty-s7/start">
+  <component name="part0" display_name="Arty S7-50" type="fpga" part_name="xc7s50csga324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/arty-s7/start">
     <interfaces>
       <interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset"> 
 		<description>DDR3 board interface, it can use MIG IP for connection.</description>

diff --git a/new/board_files/arty-z7-10/A.0/board.xml b/new/board_files/arty-z7-10/A.0/board.xml
@@ -22,14 +22,14 @@ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 SOFTWARE.
 -->
-<board schema_version="2.0" vendor="digilentinc.com" name="arty-z7-10" display_name="Arty Z7-10" url="https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start" preset_file="preset.xml" >
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-z7-10" display_name="Arty Z7-10" url="https://digilent.com/reference/programmable-logic/arty-z7/start" preset_file="preset.xml" >
 <compatible_board_revisions>
   <revision id="0">A.0</revision>
 </compatible_board_revisions>
 <file_version>1.0</file_version>
 <description>Arty Z7-10 </description>
 <components>
-  <component name="part0" display_name="Arty Z7-10" type="fpga" part_name="xc7z010clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start">
+  <component name="part0" display_name="Arty Z7-10" type="fpga" part_name="xc7z010clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="https://digilent.com/reference/programmable-logic/arty-z7/start">
     <interfaces>
       <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
         <port_maps>

diff --git a/new/board_files/arty-z7-20/A.0/board.xml b/new/board_files/arty-z7-20/A.0/board.xml
@@ -22,14 +22,14 @@ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 SOFTWARE.
 -->
-<board schema_version="2.0" vendor="digilentinc.com" name="arty-z7-20" display_name="Arty Z7-20" url="https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start" preset_file="preset.xml" >
+<board schema_version="2.0" vendor="digilentinc.com" name="arty-z7-20" display_name="Arty Z7-20" url="https://digilent.com/reference/programmable-logic/arty-z7/start" preset_file="preset.xml" >
 <compatible_board_revisions>
   <revision id="0">A.0</revision>
 </compatible_board_revisions>
 <file_version>1.0</file_version>
 <description>Arty Z7-20 </description>
 <components>
-  <component name="part0" display_name="Arty Z7-20" type="fpga" part_name="xc7z020clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start">
+  <component name="part0" display_name="Arty Z7-20" type="fpga" part_name="xc7z020clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="https://digilent.com/reference/programmable-logic/arty-z7/start">
     <interfaces>
       <interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
         <port_maps>

diff --git a/new/board_files/basys3/C.0/board.xml b/new/board_files/basys3/C.0/board.xml
@@ -22,14 +22,14 @@ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 SOFTWARE.
 -->
-<board schema_version="2.0" vendor="digilentinc.com" name="basys3" display_name="Basys3" url="https://reference.digilentinc.com/reference/programmable-logic/basys-3/start" preset_file="preset.xml">
+<board schema_version="2.0" vendor="digilentinc.com" name="basys3" display_name="Basys3" url="https://digilent.com/reference/programmable-logic/basys-3/start" preset_file="preset.xml">
 <compatible_board_revisions>
   <revision id="0">C.0</revision>
 </compatible_board_revisions>
 <file_version>1.1</file_version>
 <description>Basys3</description>
 <components>
-  <component name="part0" display_name="Basys3" type="fpga" part_name="xc7a35tcpg236-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/basys-3/start">
+  <component name="part0" display_name="Basys3" type="fpga" part_name="xc7a35tcpg236-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/basys-3/start">
     <interfaces>
       <interface mode="master" name="dip_switches_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_16bits" preset_proc="dip_switches_16bits_preset">
         <port_maps>

diff --git a/new/board_files/cmod-s7-25/B.0/board.xml b/new/board_files/cmod-s7-25/B.0/board.xml
@@ -22,14 +22,14 @@ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 SOFTWARE.
 -->
-<board schema_version="2.0" vendor="digilentinc.com" name="cmod-s7-25" display_name="Cmod S7-25" url="https://reference.digilentinc.com/reference/programmable-logic/cmod-s7/start" preset_file="preset.xml">
+<board schema_version="2.0" vendor="digilentinc.com" name="cmod-s7-25" display_name="Cmod S7-25" url="https://digilent.com/reference/programmable-logic/cmod-s7/start" preset_file="preset.xml">
     <compatible_board_revisions>
       <revision id="0">B.0</revision>
     </compatible_board_revisions>
     <file_version>1.0</file_version>
     <description>Cmod S7-25</description>
     <components>
-        <component name="part0" display_name="Cmod S7-25" type="fpga" part_name="xc7s25csga225-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/cmod-s7/start">
+        <component name="part0" display_name="Cmod S7-25" type="fpga" part_name="xc7s25csga225-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/cmod-s7/start">
             <interfaces>
                 <interface mode="slave"  name="sys_clock"          type="xilinx.com:signal:clock_rtl:1.0"        of_component="sys_clock"          preset_proc="sys_clock_preset">
                     <description>12 MHz Single-Ended System Clock</description>

diff --git a/new/board_files/cmod_a7-15t/B.0/board.xml b/new/board_files/cmod_a7-15t/B.0/board.xml
@@ -22,14 +22,14 @@ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 SOFTWARE.
 -->
-<board schema_version="2.0" vendor="digilentinc.com" name="cmod_a7-15t" display_name="Cmod A7-15t" url="https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/start" preset_file="preset.xml">
+<board schema_version="2.0" vendor="digilentinc.com" name="cmod_a7-15t" display_name="Cmod A7-15t" url="https://digilent.com/reference/programmable-logic/cmod-a7/start" preset_file="preset.xml">
 <compatible_board_revisions>
   <revision id="0">B.0</revision>
 </compatible_board_revisions>
 <file_version>1.1</file_version>
 <description>Cmod A7-15t</description>
 <components>
-  <component name="part0" display_name="Cmod A7-15t" type="fpga" part_name="xc7a15tcpg236-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/start">
+  <component name="part0" display_name="Cmod A7-15t" type="fpga" part_name="xc7a15tcpg236-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/cmod-a7/start">
     <interfaces>
 	<interface mode="master" name="cellular_ram" type="xilinx.com:interface:emc_rtl:1.0" of_component="cellular_ram" preset_proc="sram_preset">
         <description>512KB SRAM</description>

diff --git a/new/board_files/cmod_a7-35t/B.0/board.xml b/new/board_files/cmod_a7-35t/B.0/board.xml
@@ -22,14 +22,14 @@ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 SOFTWARE.
 -->
-<board schema_version="2.0" vendor="digilentinc.com" name="cmod_a7-35t" display_name="Cmod A7-35t" url="https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/start" preset_file="preset.xml">
+<board schema_version="2.0" vendor="digilentinc.com" name="cmod_a7-35t" display_name="Cmod A7-35t" url="https://digilent.com/reference/programmable-logic/cmod-a7/start" preset_file="preset.xml">
 <compatible_board_revisions>
   <revision id="0">B.0</revision>
 </compatible_board_revisions>
 <file_version>1.1</file_version>
 <description>Cmod A7-35t</description>
 <components>
-  <component name="part0" display_name="Cmod A7-35t" type="fpga" part_name="xc7a35tcpg236-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/start">
+  <component name="part0" display_name="Cmod A7-35t" type="fpga" part_name="xc7a35tcpg236-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/cmod-a7/start">
     <interfaces>
 	<interface mode="master" name="cellular_ram" type="xilinx.com:interface:emc_rtl:1.0" of_component="cellular_ram" preset_proc="sram_preset">
         <description>512KB SRAM</description>

diff --git a/new/board_files/cora-z7-07s/B.0/board.xml b/new/board_files/cora-z7-07s/B.0/board.xml
@@ -22,14 +22,14 @@ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 SOFTWARE.
 -->
-<board schema_version="2.0" vendor="digilentinc.com" name="cora-z7-07s" display_name="Cora Z7-07S" url="https://reference.digilentinc.com/reference/programmable-logic/cora-z7/start" preset_file="preset.xml" >
+<board schema_version="2.0" vendor="digilentinc.com" name="cora-z7-07s" display_name="Cora Z7-07S" url="https://digilent.com/reference/programmable-logic/cora-z7/start" preset_file="preset.xml" >
 	<compatible_board_revisions>
 		<revision id="0">B.0</revision>
 	</compatible_board_revisions>
 	<file_version>1.0</file_version>
 	<description>Cora Z7-07S</description>
 	<components>
-		<component name="part0" display_name="Cora Z7-07S" type="fpga" part_name="xc7z007sclg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="https://reference.digilentinc.com/reference/programmable-logic/cora-z7/start">
+		<component name="part0" display_name="Cora Z7-07S" type="fpga" part_name="xc7z007sclg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="https://digilent.com/reference/programmable-logic/cora-z7/start">
 			<interfaces>
 				<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"> 
 				</interface>

diff --git a/new/board_files/cora-z7-10/B.0/board.xml b/new/board_files/cora-z7-10/B.0/board.xml
@@ -22,14 +22,14 @@ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 SOFTWARE.
 -->
-<board schema_version="2.0" vendor="digilentinc.com" name="cora-z7-10" display_name="Cora Z7-10" url="https://reference.digilentinc.com/reference/programmable-logic/cora-z7/start" preset_file="preset.xml" >
+<board schema_version="2.0" vendor="digilentinc.com" name="cora-z7-10" display_name="Cora Z7-10" url="https://digilent.com/reference/programmable-logic/cora-z7/start" preset_file="preset.xml" >
 	<compatible_board_revisions>
 		<revision id="0">B.0</revision>
 	</compatible_board_revisions>
 	<file_version>1.0</file_version>
 	<description>Cora Z7-10</description>
 	<components>
-		<component name="part0" display_name="Cora Z7-10" type="fpga" part_name="xc7z010clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="https://reference.digilentinc.com/reference/programmable-logic/cora-z7/start">
+		<component name="part0" display_name="Cora Z7-10" type="fpga" part_name="xc7z010clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="https://digilent.com/reference/programmable-logic/cora-z7/start">
 			<interfaces>
 				<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"> 
 				</interface>

diff --git a/new/board_files/eclypse-z7/B.0/board.xml b/new/board_files/eclypse-z7/B.0/board.xml
@@ -22,7 +22,7 @@ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 SOFTWARE.
 -->
-<board schema_version="2.0" vendor="digilentinc.com" name="eclypse-z7" display_name="Eclypse Z7" url="https://www.digilentinc.com" preset_file="preset.xml">
+<board schema_version="2.0" vendor="digilentinc.com" name="eclypse-z7" display_name="Eclypse Z7" url="https://digilent.com/reference/programmable-logic/eclypse-z7/start" preset_file="preset.xml">
 <compatible_board_revisions>
 	<revision id="0">B.0</revision>
 </compatible_board_revisions>
@@ -31,7 +31,7 @@ SOFTWARE.
 
 <components>
 	<!-- Defines BD interfaces that can be used to connect the FPGA to a particular <component> -->
-	<component name="part0" display_name="Eclypse Z7" type="fpga" part_name="xc7z020clg484-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.digilentinc.com">
+	<component name="part0" display_name="Eclypse Z7" type="fpga" part_name="xc7z020clg484-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/eclypse-z7/start">
 		<interfaces> 
 			<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
 				<port_maps>

diff --git a/new/board_files/genesys-zu-3eg/D.0/board.xml b/new/board_files/genesys-zu-3eg/D.0/board.xml
@@ -22,7 +22,7 @@ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 SOFTWARE.
 -->
-<board schema_version="2.1" vendor="digilentinc.com" name="gzu_3eg" display_name="Genesys ZU-3EG" url="https://www.digilentinc.com" preset_file="preset.xml">
+<board schema_version="2.1" vendor="digilentinc.com" name="gzu_3eg" display_name="Genesys ZU-3EG" url="https://digilent.com/reference/programmable-logic/genesys-zu/start" preset_file="preset.xml">
 <compatible_board_revisions>
 	<revision id="0">D.0</revision>
 </compatible_board_revisions>
@@ -31,7 +31,7 @@ SOFTWARE.
 
 <components>
 	<!-- Defines BD interfaces that can be used to connect the FPGA to a particular <component> -->
-	<component name="part0" display_name="Genesys ZU-3EG" type="fpga" part_name="xczu3eg-sfvc784-1-e" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.digilentinc.com">
+	<component name="part0" display_name="Genesys ZU-3EG" type="fpga" part_name="xczu3eg-sfvc784-1-e" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/genesys-zu/start">
 		<interfaces>
 			<interface mode="master" name="ps8_fixedio" type="xilinx.com:zynq_ultra_ps_e:fixedio_rtl:1.0" of_component="ps8_fixedio" preset_proc="zynq_ultra_ps_e_preset"> 
 				<preferred_ips>