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Commits on Jan 3, 2025

• Update copyright years for 2025 release to XilinxBoardStore

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Commits on Sep 8, 2023

• Merge pull request #44 from emb4fun/bugfix_zybo

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Commits on Aug 26, 2023

• Corrected CPU PLL settings

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Commits on Jan 11, 2023

• Update Zedboard PS input clock frequency

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Commits on Dec 31, 2022

• Fix swapped Nexys A7 Accelerometer MOSI/MISO pins

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Commits on Mar 25, 2022

• Update reference links in readme

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Commits on Mar 4, 2022

• Increment file versions

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Commits on Mar 3, 2022

• Nexys A7-50T: Re-add version 1.0 from commit 8b56d97.

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• Nexys A7-50T: Increment to 1.2 with both MIG changes and linter fixes

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• NexysA7-50T:Resolved issues at mig

  

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• ZU-3EG Rev B.0: Update URLs

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• Most boards: Update URLs to point to digilent.com/reference and resource centers

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• Nexys Video: Change PHY reset description and fix reset logical ports to clear linter warning

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• Nexys A7: Remove nonfunctional ethernet interfaces

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Commits on Mar 2, 2022

• Genesys 2: Remove button label annotations that made the pins xml invalid

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• Genesys 2 and Sword: Remove invalid empty IP presets

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• Genesys 2: Cut DSPI interface incorrectly specified as master

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Commits on Feb 24, 2022

• Capitalize clock_rtl logical_ports in order to clear validation script warnings

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Commits on Feb 12, 2022

• USB104 A7: Remove illegal preferred_ips tag from UART component

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• Zedboard: Add missing IP end tag

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Commits on Feb 11, 2022

• Add licenses to usb104 1.3, ZU-5EV, and ZU-3EG

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• usb104-a7: Add version 1.3 implementing a reset on button 0

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• Add root-level license

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• Add Licenses

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• The lack of a user_parameters or model_parameters element is invalid, and appears to have no effect on whether the axi_ethernetlite IP is presented as a selection option. Warrants further testing.

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• The preferred_ips element is not valid in the component

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• Correct CLK port capitalization to match clock_rtl's interface definition

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• Add missing user_parameters end tag.

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• Remove duplicate ip_preset end tag.

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• Remove do-nothing presets for vivado-library's PWM 2.0 IP.

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• Arty S7-50: Correct MIG sys_clk pad name

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• Nexys Video: Add version 1.2 with MIG configured for ui_addn_clk_0 looped back to ref_clk and external sys_clk.

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• Nexys Video: Move board files to folder 1.1 to allow additional versions

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• Nexys A7-100T: Add version 1.1 with updated version of MIG intended for ref_clk looped back from ui_addn_clk_0.

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• Nexys Video and A7-100T: Move existing into 1.0 folders to allow additional versions alongside.

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