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decodes continuous manchester data stream, measures bit-time
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@mozerj2001
mozerj2001 committed Mar 12, 2022
1 parent 658e380 commit f9ca9a7
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108 changes: 63 additions & 45 deletions mvb-stack-hardware/manchester_decoder.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity manchester_decoder is
entity e_MANCHESTER_DECODER is
Port ( clk_xx : in std_logic; -- 16x clock input for clock recovery and oversampling
rst : in std_logic;
rdn : in std_logic; -- control signal initiates read operation
Expand All @@ -14,9 +14,9 @@ entity manchester_decoder is
data_ready : out std_logic; -- indicates that the decoded_out data is ready
decode_error : out std_logic -- an error has occured in the decode process (e. g. there was no edge mid-bit)
);
end manchester_decoder;
end e_MANCHESTER_DECODER;

architecture Behavioral of manchester_decoder is
architecture Behavioral of e_MANCHESTER_DECODER is

constant MVB_WORD_WIDTH : integer := 16; -- MVB data word width is per industry standard 16 bits
constant OVERSAMPLING_FACTOR : integer := 16; -- oversampling factor
Expand All @@ -28,76 +28,94 @@ constant SAMPLING_COUNTER_WIDTH : integer := 4; -- width of the counter, ba
---------------------------------------------------------------

-- internal shift register for decoded input, value of current decoded bit
signal man_data_in_shr : std_logic_vector(7 downto 0);
signal current_bit_decoded : std_logic;

-- register for edge direction detection
signal input_edge_register : std_logic_vector(1 downto 0);

-- counter for sampling at 25% clk and 75% clk and sample enable signal
signal fourth_counter : unsigned(SAMPLING_COUNTER_WIDTH-1 downto 0);
signal fourth_counter_at_edge : unsigned(SAMPLING_COUNTER_WIDTH-1 downto 0) := to_unsigned(2**SAMPLING_COUNTER_WIDTH - 1, SAMPLING_COUNTER_WIDTH); -- register to save counter value at edge for sync
signal sample_manchester_input : std_logic;
--variable sample_at_25 : boolean;
--variable sample_at_75 : boolean;
signal sample_at_25 : std_logic := '0';
signal sample_at_75 : std_logic := '1';
signal r_MAN_DATA_IN_SHIFT : std_logic_vector(7 downto 0);
signal r_CURRENT_BIT_DECODED : std_logic;

-- registers and signals for bit time measurement
signal r_INPUT_BIT_TIME_SHIFT : std_logic_vector(1 downto 0);
signal r_SAMPLING_COUNTER_AT_HALF_BIT : unsigned(SAMPLING_COUNTER_WIDTH-1 downto 0) := to_unsigned(2**SAMPLING_COUNTER_WIDTH - 1, SAMPLING_COUNTER_WIDTH); -- register to save counter value at edge for sync
signal s_IN_BIT_MIDDLE : std_logic := '0';
signal s_AT_EDGE : std_logic := '0';

-- registers and signals for determining current bit value
signal r_INPUT_EDGE_SHIFT : std_logic_vector(1 downto 0);
signal r_SAMPLING_COUNTER : unsigned(SAMPLING_COUNTER_WIDTH-1 downto 0);
signal s_SAMPLE_MANCHESTER_INPUT : std_logic;
signal s_SAMPLE_AT_25 : std_logic := '0';
signal s_SAMPLE_AT_75 : std_logic := '1';

---------------------------------------------------------------
------------------- BEHAVIORAL DESCRIPTION --------------------
---------------------------------------------------------------
begin
-- get input bit into shift register
process(rst, sample_manchester_input)
-- get input bit into shift register on every sample enable signal (bit value detection)
p_DETECT_IN_BIT_STATE_CHANGE : process(clk_xx)
begin
if(rst = '1') then
input_edge_register <= "00";
elsif(sample_manchester_input = '1') then
input_edge_register <= (input_edge_register(0) & manchester_in);
if(rising_edge(clk_xx)) then
if(rst = '1') then
r_INPUT_EDGE_SHIFT <= "00";
elsif(s_SAMPLE_MANCHESTER_INPUT = '1') then
r_INPUT_EDGE_SHIFT <= (r_INPUT_EDGE_SHIFT(0) & manchester_in);
else
end if;
else
end if;
end process;
end process p_DETECT_IN_BIT_STATE_CHANGE;

-- detect edge as close to the edge as possible, to measure half bit-time
s_IN_BIT_MIDDLE <= '1' when ((r_SAMPLING_COUNTER > to_unsigned(OVERSAMPLING_FACTOR/4, SAMPLING_COUNTER_WIDTH)) and (r_SAMPLING_COUNTER < to_unsigned(OVERSAMPLING_FACTOR*3/4, SAMPLING_COUNTER_WIDTH))) else '0';
s_AT_EDGE <= '1' when ((r_INPUT_BIT_TIME_SHIFT = "10") or (r_INPUT_BIT_TIME_SHIFT = "01")) else '0';

p_DETECT_BIT_TIME : process(clk_xx)
begin
if(rising_edge(clk_xx)) then
if(rst = '1') then
r_INPUT_BIT_TIME_SHIFT <= "00";
else
r_INPUT_BIT_TIME_SHIFT <= (r_INPUT_BIT_TIME_SHIFT(0) & manchester_in);
end if;
end if;
if((s_IN_BIT_MIDDLE = '1') and (s_AT_EDGE = '1')) then
r_SAMPLING_COUNTER_AT_HALF_BIT <= r_SAMPLING_COUNTER;
end if;
end process p_DETECT_BIT_TIME;

-- create counter, based on which sampling times can be determined,
-- save currently decoded bit value when the clock cycle comes to an end (LSB FIRST)
process(clk_xx)
p_SAMPLING_COUNTER : process(clk_xx)
begin
if(rising_edge(clk_xx)) then
if(rst = '1') then
fourth_counter <= to_unsigned(0, SAMPLING_COUNTER_WIDTH);
man_data_in_shr(7 downto 0) <= "00000000";
elsif(fourth_counter = fourth_counter_at_edge) then
fourth_counter <= to_unsigned(0, SAMPLING_COUNTER_WIDTH);
man_data_in_shr(7 downto 0) <= (current_bit_decoded & man_data_in_shr(7 downto 1));
r_SAMPLING_COUNTER <= to_unsigned(0, SAMPLING_COUNTER_WIDTH);
r_MAN_DATA_IN_SHIFT(7 downto 0) <= "00000000";
-- reset on the measured bit-width (-5 is needed, because the value read is delayed by two cycles, and the delay is doubled)
elsif(r_SAMPLING_COUNTER = (2*r_SAMPLING_COUNTER_AT_HALF_BIT-5)) then
r_SAMPLING_COUNTER <= to_unsigned(0, SAMPLING_COUNTER_WIDTH);
r_MAN_DATA_IN_SHIFT(7 downto 0) <= (r_CURRENT_BIT_DECODED & r_MAN_DATA_IN_SHIFT(7 downto 1));
else
fourth_counter <= fourth_counter + 1;
r_SAMPLING_COUNTER <= r_SAMPLING_COUNTER + 1;
end if;
end if;
end process;
end process p_SAMPLING_COUNTER;

-- get edge direction of current bit, save value according to the manchester coding standard
-- save the value of the sampling counter for synchronization purposes
p_DETECT_EDGE : process (input_edge_register)
p_DECODE_BIT_VALUE : process (r_INPUT_EDGE_SHIFT)
begin
case input_edge_register is
case r_INPUT_EDGE_SHIFT is
when "10" =>
current_bit_decoded <= '1';
r_CURRENT_BIT_DECODED <= '1';
when "01" =>
current_bit_decoded <= '0';
r_CURRENT_BIT_DECODED <= '0';
when others =>
end case;
if((fourth_counter > to_unsigned(OVERSAMPLING_FACTOR/4, SAMPLING_COUNTER_WIDTH)) and (fourth_counter < to_unsigned(OVERSAMPLING_FACTOR*3/4, SAMPLING_COUNTER_WIDTH))) then
fourth_counter_at_edge <= fourth_counter;
end if;
end process p_DETECT_EDGE;
end process p_DECODE_BIT_VALUE;


-- sample value at clk3 and clk11 (at 25% and 75%)
--sample_at_25 := (fourth_counter = to_unsigned(OVERSAMPLING_FACTOR/4, SAMPLING_COUNTER_WIDTH));
--sample_at_75 := (fourth_counter = to_unsigned(OVERSAMPLING_FACTOR*3/4, SAMPLING_COUNTER_WIDTH));
sample_at_25 <= '1' when (fourth_counter = to_unsigned(OVERSAMPLING_FACTOR/4, SAMPLING_COUNTER_WIDTH)) else '0';
sample_at_75 <= '1' when (fourth_counter = to_unsigned(OVERSAMPLING_FACTOR*3/4, SAMPLING_COUNTER_WIDTH)) else '0';
sample_manchester_input <= '1' when (sample_at_25 = '1') or (sample_at_75 = '1') else '0';
s_SAMPLE_AT_25 <= '1' when (r_SAMPLING_COUNTER = to_unsigned(OVERSAMPLING_FACTOR/4, SAMPLING_COUNTER_WIDTH)) else '0';
s_SAMPLE_AT_75 <= '1' when (r_SAMPLING_COUNTER = to_unsigned(OVERSAMPLING_FACTOR*3/4, SAMPLING_COUNTER_WIDTH)) else '0';
s_SAMPLE_MANCHESTER_INPUT <= '1' when (s_SAMPLE_AT_25 = '1') or (s_SAMPLE_AT_75 = '1') else '0';

end Behavioral;

34 changes: 23 additions & 11 deletions mvb-stack-hardware/mvb-stack-hardware.gise
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Original file line number Diff line number Diff line change
Expand Up @@ -22,8 +22,13 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="mvb-stack-hardware.xise"/>

<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="e_MANCHESTER_DECODER_isim_beh.exe"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="manchester_decoder_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testbench_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testbench_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testbench_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
Expand All @@ -34,40 +39,47 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
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<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="manchester_decoder.vhd"/>
<outfile xil_pn:name="test_manchester_decoder.vhd"/>
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</transforms>
Expand Down
16 changes: 8 additions & 8 deletions mvb-stack-hardware/mvb-stack-hardware.xise
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Original file line number Diff line number Diff line change
Expand Up @@ -141,9 +141,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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Expand Down Expand Up @@ -206,7 +206,7 @@
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Expand All @@ -219,10 +219,10 @@
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Expand All @@ -244,7 +244,7 @@
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Expand Down
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