Reverted controller key change, fixed enc/dec mismatch in decoupler.

Elena32061 · Mar 19, 2021 · 2ce22b6 · 2ce22b6
1 parent bd50f31
commit 2ce22b6
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Showing 2 changed files with 3 additions and 4 deletions.
diff --git a/src/main/scala/controller.scala b/src/main/scala/controller.scala
@@ -330,8 +330,7 @@ class AESController(addrBits: Int, beatBytes: Int)(implicit p: Parameters) exten
       }
       // TODO: how does key/text lay out across the memory?
       when (cState === AESState.sKeySetup) {
-//        io.aesCoreIO.address := AESAddr.KEY + mem_target_reg - 1.U  - counter_reg
-        io.aesCoreIO.address := AESAddr.KEY + 7.U  - counter_reg
+        io.aesCoreIO.address := AESAddr.KEY + mem_target_reg - 1.U  - counter_reg
         io.testAESWriteData.bits := ((AESAddr.KEY + mem_target_reg - 1.U  - counter_reg) << 32) + dequeue.io.dataOut.bits
       } .elsewhen (cState === AESState.sDataSetup) {
         io.aesCoreIO.address := AESAddr.TEXT + 3.U - counter_reg

diff --git a/src/main/scala/decoupler.scala b/src/main/scala/decoupler.scala
@@ -67,11 +67,11 @@ class RoCCDecoupler(implicit p: Parameters) extends Module {
       dest_addr_reg  := rs2_data
     } .elsewhen ((funct === 3.U(7.W)) & ~start_valid_reg) {
       start_valid_reg := true.B
-      op_type_reg     := 0.U(1.W)
+      op_type_reg     := 1.U(1.W)
       block_count_reg := rs1_data
     } .elsewhen ((funct === 4.U(7.W)) & ~start_valid_reg) {
       start_valid_reg := true.B
-      op_type_reg     := 1.U(1.W)
+      op_type_reg     := 0.U(1.W)
       block_count_reg := rs1_data
     } .elsewhen ((funct === 5.U(7.W)) & ~resp_valid_reg) {
       resp_rd_reg    := rd