Elena32061
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Paper_Plot_Python Public
This repository contains a collection of plotting scripts that I have used or might use for creating figures in academic reserch papers.
Python UpdatedNov 19, 2024 -
Quest Public
Forked from mit-han-lab/Quest[ICML 2024] Quest: Query-Aware Sparsity for Efficient Long-Context LLM Inference
Cuda UpdatedOct 9, 2024 -
streaming-llm Public
Forked from mit-han-lab/streaming-llm[ICLR 2024] Efficient Streaming Language Models with Attention Sinks
Python MIT License UpdatedJul 11, 2024 -
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Python-100-Days Public
Forked from jackfrued/Python-100-DaysPython - 100天从新手到大师
Python UpdatedDec 27, 2022 -
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ravenoc Public
Forked from aignacio/ravenocRaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
SystemVerilog MIT License UpdatedJul 6, 2022 -
chisel-tutorial Public
Forked from ucb-bar/chisel-tutorialchisel tutorial exercises and answers
Scala Other UpdatedJan 6, 2022 -
CornellCSWiki Public
Forked from CornellCSWiki/CornellCSWikiStudent-run wiki for students interested in computer science at Cornell University
CSS Creative Commons Attribution Share Alike 4.0 International UpdatedJan 4, 2022 -
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AAML-f21 Public
Forked from BoWeii/AAML-f21Accelerator Architectures for Machine Learning homework NYCU 2021
C++ UpdatedDec 10, 2021 -
scale-sim-v2 Public
Forked from scalesim-project/scale-sim-v2Repository to host and maintain scale-sim-v2 code
Python UpdatedNov 16, 2021 -
Useful-Academic-Links Public
Forked from Nitesh8998/Useful-Academic-LinksThis repo has some usefull links to websites for topics, please fork add and generate a pull-request to join the party
UpdatedNov 12, 2021 -
sp21-aes-rocc-accel Public
Forked from ucb-ee290c/sp21-aes-rocc-accelAES RoCC Accelerator
Scala BSD 3-Clause "New" or "Revised" License UpdatedJul 24, 2021 -
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esp-isa-sim Public
Forked from ucb-bar/esp-isa-simCustom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
C Other UpdatedMay 6, 2021 -
gitqwerty777.github.io Public
Forked from gitqwerty777/gitqwerty777.github.ioUsed for a site
HTML UpdatedApr 27, 2021 -
Systolic-array-implementation-in-RTL-for-TPU Public
Forked from abdelazeem201/Systolic-array-implementation-in-RTL-for-TPUIC implementation of Systolic Array for TPU
Verilog MIT License UpdatedJan 8, 2021 -
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tptpu-sim Public
Forked from jinhachung/tptpu-simA Toy-Purpose TPU Simulator
C++ UpdatedAug 19, 2019 -
Verilog-Code-of-Synchronus-FIFO-Design-with-verilog-test-code Public
Forked from Danishazmi29/Verilog-Code-of-Synchronus-FIFO-Design-with-verilog-test-codeA FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. There are many other use of FIFO also. FIFO uses a dual port me…
Verilog UpdatedNov 5, 2017