The UVM written in Python

challenges-EngRaff92 forked

A simple RISC V core for teaching

Hardware generation library based on "Kernel IP" (KIP) cores (microarchitectural programmable templates)

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA.

User-friendly explanation of Yosys options

Unit testing for cocotb

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.

A Pipelined RISC-V RV32I Core in SystemVerilog

Learning FPGA, yosys, nextpnr, and RISC-V

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

Common SystemVerilog components

APB Logic

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Random instruction generator for RISC-V processor verification

OpenTitan: Open source silicon root of trust

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Computer architecture learning environment using FPGAs

Naive Educational RISC V processor