Skip to content
View EvgenevKI's full-sized avatar

Block or report EvgenevKI

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

GoodbyeDPI — Deep Packet Inspection circumvention utility (for Windows)

C 26,425 1,964 Updated Nov 6, 2024

超迷你模块化卡片电脑计划

3,211 801 Updated Jul 25, 2022

低成本(RMB 7元左右)12V的bldc驱动电路。基于STC15W401AS单片机。

C 26 14 Updated Jul 6, 2018

stm32f4を用いたジンバルPID制御用プログラム。

C 4 2 Updated Jun 18, 2020

Custom PCB design and firmware, which serve as a ESC or BLDC controller, to drive brushless BLDC motors using my own control algorithms.

C 71 14 Updated Apr 8, 2022

Personal schematic symbol and footprint libraries for Altium Designer.

171 36 Updated Jul 24, 2023

Test PCB for switching regulator layout and traces.

C 35 9 Updated May 21, 2022

Learn FPGA Programming, published by Packt, Russian translate. Программирование FPGA для начинающих

VHDL 1 1 Updated Jun 13, 2022
Verilog 10 4 Updated May 4, 2020

Intel DPRAM ip project

VHDL 1 Updated Sep 20, 2022

Configuring Audio Codec WM8731 via I2C

Tcl 1 Updated Feb 24, 2022

Audio input and output and FIR Filter implemented

VHDL 1 1 Updated Jan 25, 2022

This project is an practical implementation of FPGA based FSK modulator on DE2-115 development board

VHDL 1 Updated Nov 18, 2021

LCD Driver in VHDL

Tcl 2 Updated Nov 17, 2021
Tcl 2 Updated Nov 15, 2021

VUnit is a unit testing framework for VHDL/SystemVerilog

VHDL 1 Updated Oct 23, 2021

SPI Master and Slave components to be used in all of FPGAs, written in VHDL.

VHDL 1 Updated Apr 17, 2020

training labs and examples

SystemVerilog 1 Updated Jul 13, 2017
VHDL 2 Updated Nov 15, 2021

FPGA Implementation of OTDR for analysis of fiber optic network . The memory used is ZBT Ram ( Zero Bus Turnaround)

VHDL 14 2 Updated Nov 17, 2021

URDF model for the Rhea wheeled biped

Python 266 19 Updated Feb 21, 2024

Arduino and python code for a mini-radio telescope.

Jupyter Notebook 338 38 Updated Feb 19, 2023

Microwave imaging using Tailgater portable satellite antenna

Python 89 15 Updated May 3, 2023