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Made runner a std_logic_vector
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LarsAsplund committed Jul 29, 2018
1 parent 2f9b141 commit 0a462f4
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Showing 13 changed files with 53 additions and 49 deletions.
3 changes: 2 additions & 1 deletion vunit/vhdl/check/test/tb_check.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,7 @@ use vunit_lib.checker_pkg.all;
use vunit_lib.check_pkg.all;
use vunit_lib.run_types_pkg.all;
use vunit_lib.run_pkg.all;
use vunit_lib.runner_pkg.all;
use work.test_support.all;
use ieee.numeric_std.all;
entity tb_check is
Expand All @@ -36,7 +37,7 @@ architecture test_fixture of tb_check is
begin
clock: process is
begin
while runner.phase < test_runner_exit loop
while get_phase(runner_state) < test_runner_exit loop
clk <= '1', '0' after 5 ns;
wait for 10 ns;
end loop;
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3 changes: 2 additions & 1 deletion vunit/vhdl/check/test/tb_check_false.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ use ieee.std_logic_1164.all;
library vunit_lib;
use vunit_lib.run_types_pkg.all;
use vunit_lib.run_pkg.all;
use vunit_lib.runner_pkg.all;
use vunit_lib.log_levels_pkg.all;
use vunit_lib.logger_pkg.all;
use vunit_lib.checker_pkg.all;
Expand All @@ -36,7 +37,7 @@ architecture test_fixture of tb_check_false is
begin
clock: process is
begin
while runner.phase < test_runner_exit loop
while get_phase(runner_state) < test_runner_exit loop
clk <= '1', '0' after 5 ns;
wait for 10 ns;
end loop;
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3 changes: 2 additions & 1 deletion vunit/vhdl/check/test/tb_check_implication.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ use ieee.std_logic_1164.all;
library vunit_lib;
use vunit_lib.run_types_pkg.all;
use vunit_lib.run_pkg.all;
use vunit_lib.runner_pkg.all;
use vunit_lib.log_levels_pkg.all;
use vunit_lib.logger_pkg.all;
use vunit_lib.checker_pkg.all;
Expand Down Expand Up @@ -47,7 +48,7 @@ architecture test_fixture of tb_check_implication is
begin
clock: process is
begin
while runner.phase < test_runner_exit loop
while get_phase(runner_state) < test_runner_exit loop
clk <= '1', '0' after 5 ns;
wait for 10 ns;
end loop;
Expand Down
3 changes: 2 additions & 1 deletion vunit/vhdl/check/test/tb_check_next.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ use ieee.std_logic_1164.all;
library vunit_lib;
use vunit_lib.run_types_pkg.all;
use vunit_lib.run_pkg.all;
use vunit_lib.runner_pkg.all;
use vunit_lib.log_levels_pkg.all;
use vunit_lib.logger_pkg.all;
use vunit_lib.checker_pkg.all;
Expand Down Expand Up @@ -59,7 +60,7 @@ architecture test_fixture of tb_check_next is
begin
clock: process is
begin
while runner.phase < test_runner_exit loop
while get_phase(runner_state) < test_runner_exit loop
clk <= '1', '0' after 5 ns;
wait for 10 ns;
end loop;
Expand Down
3 changes: 2 additions & 1 deletion vunit/vhdl/check/test/tb_check_not_unknown.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ use ieee.std_logic_1164.all;
library vunit_lib;
use vunit_lib.run_types_pkg.all;
use vunit_lib.run_pkg.all;
use vunit_lib.runner_pkg.all;
use vunit_lib.log_levels_pkg.all;
use vunit_lib.logger_pkg.all;
use vunit_lib.checker_pkg.all;
Expand Down Expand Up @@ -51,7 +52,7 @@ architecture test_fixture of tb_check_not_unknown is
begin
clock: process is
begin
while runner.phase < test_runner_exit loop
while get_phase(runner_state) < test_runner_exit loop
clk <= '1', '0' after 5 ns;
wait for 10 ns;
end loop;
Expand Down
3 changes: 2 additions & 1 deletion vunit/vhdl/check/test/tb_check_one_hot.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ use ieee.std_logic_1164.all;
library vunit_lib;
use vunit_lib.run_types_pkg.all;
use vunit_lib.run_pkg.all;
use vunit_lib.runner_pkg.all;
use vunit_lib.log_levels_pkg.all;
use vunit_lib.logger_pkg.all;
use vunit_lib.checker_pkg.all;
Expand All @@ -34,7 +35,7 @@ architecture test_fixture of tb_check_one_hot is
begin
clock: process is
begin
while runner.phase < test_runner_exit loop
while get_phase(runner_state) < test_runner_exit loop
clk <= '1', '0' after 5 ns;
wait for 10 ns;
end loop;
Expand Down
3 changes: 2 additions & 1 deletion vunit/vhdl/check/test/tb_check_sequence.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ use ieee.std_logic_1164.all;
library vunit_lib;
use vunit_lib.run_types_pkg.all;
use vunit_lib.run_pkg.all;
use vunit_lib.runner_pkg.all;
use vunit_lib.log_levels_pkg.all;
use vunit_lib.logger_pkg.all;
use vunit_lib.checker_pkg.all;
Expand Down Expand Up @@ -40,7 +41,7 @@ architecture test_fixture of tb_check_sequence is
begin
clock: process is
begin
while runner.phase < test_runner_exit loop
while get_phase(runner_state) < test_runner_exit loop
clk <= '1', '0' after 5 ns;
wait for 10 ns;
end loop;
Expand Down
3 changes: 2 additions & 1 deletion vunit/vhdl/check/test/tb_check_stable.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ use ieee.std_logic_1164.all;
library vunit_lib;
use vunit_lib.run_types_pkg.all;
use vunit_lib.run_pkg.all;
use vunit_lib.runner_pkg.all;
use vunit_lib.log_levels_pkg.all;
use vunit_lib.logger_pkg.all;
use vunit_lib.checker_pkg.all;
Expand Down Expand Up @@ -80,7 +81,7 @@ architecture test_fixture of tb_check_stable is
begin
clock : process is
begin
while runner.phase < test_runner_exit loop
while get_phase(runner_state) < test_runner_exit loop
clk <= '1', '0' after 5 ns;
wait for 10 ns;
end loop;
Expand Down
3 changes: 2 additions & 1 deletion vunit/vhdl/check/test/tb_check_zero_one_hot.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ use ieee.std_logic_1164.all;
library vunit_lib;
use vunit_lib.run_types_pkg.all;
use vunit_lib.run_pkg.all;
use vunit_lib.runner_pkg.all;
use vunit_lib.log_levels_pkg.all;
use vunit_lib.logger_pkg.all;
use vunit_lib.checker_pkg.all;
Expand All @@ -34,7 +35,7 @@ architecture test_fixture of tb_check_zero_one_hot is
begin
clock: process is
begin
while runner.phase < test_runner_exit loop
while get_phase(runner_state) < test_runner_exit loop
clk <= '1', '0' after 5 ns;
wait for 10 ns;
end loop;
Expand Down
20 changes: 10 additions & 10 deletions vunit/vhdl/run/src/run.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -19,10 +19,10 @@ use std.textio.all;
package body run_pkg is
procedure notify(signal runner : inout runner_sync_t) is
begin
if runner.event /= runner_event then
runner.event <= runner_event;
wait until runner.event = runner_event;
runner.event <= idle_runner;
if runner(runner_event_idx) /= runner_event then
runner(runner_event_idx) <= runner_event;
wait until runner(runner_event_idx) = runner_event;
runner(runner_event_idx) <= idle_runner;
end if;
end procedure notify;

Expand Down Expand Up @@ -56,9 +56,9 @@ package body run_pkg is
end if;

set_phase(runner_state, test_runner_setup);
runner(runner_exit_status_idx) <= runner_exit_with_errors;
notify(runner);
runner.exit_without_errors <= false;
wait for 0 ns;

trace(runner_trace_logger, "Entering test runner setup phase.");
entry_gate(runner);

Expand Down Expand Up @@ -121,8 +121,8 @@ package body run_pkg is
return;
end if;

runner.exit_without_errors <= true;
wait for 0 ns;
runner(runner_exit_status_idx) <= runner_exit_without_errors;
notify(runner);

if has_active_python_runner(runner_state) then
core_pkg.test_suite_done;
Expand Down Expand Up @@ -279,8 +279,8 @@ package body run_pkg is
signal runner : inout runner_sync_t;
constant timeout : in time) is
begin
wait until runner.exit_without_errors for timeout;
if not runner.exit_without_errors then
wait until runner(runner_exit_status_idx) = runner_exit_without_errors for timeout;
if not (runner(runner_exit_status_idx) = runner_exit_without_errors) then
error(runner_trace_logger, "Test runner timeout after " & time'image(timeout) & ".");
test_runner_cleanup(runner);
end if;
Expand Down
6 changes: 2 additions & 4 deletions vunit/vhdl/run/src/run_api.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -15,13 +15,11 @@ library ieee;
use ieee.std_logic_1164.all;

package run_pkg is
signal runner : runner_sync_t := (event => idle_runner,
exit_without_errors => false);
signal runner : runner_sync_t := (runner_event_idx => idle_runner,
runner_exit_status_idx => runner_exit_with_errors);

constant runner_state : runner_t := new_runner;

procedure notify(signal runner : inout runner_sync_t);

procedure test_runner_setup (
signal runner : inout runner_sync_t;
constant runner_cfg : in string := runner_cfg_default);
Expand Down
28 changes: 7 additions & 21 deletions vunit/vhdl/run/src/run_types.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -35,32 +35,18 @@ package run_types_pkg is
end record;

type boolean_array_t is array (integer range <>) of boolean;
function resolve_runner_flag (
constant values : boolean_array_t)
return boolean;
subtype runner_flag_t is resolve_runner_flag boolean;

constant runner_event_idx : natural := 0;
constant runner_exit_status_idx : natural := 1;

constant runner_event : std_logic := '1';
constant idle_runner : std_logic := 'Z';

type runner_sync_t is record
event : std_logic;
exit_without_errors : runner_flag_t;
end record runner_sync_t;
constant runner_exit_with_errors : std_logic := 'Z';
constant runner_exit_without_errors : std_logic := '1';

subtype runner_sync_t is std_logic_vector(runner_event_idx to runner_exit_status_idx);
end package;

package body run_types_pkg is
function resolve_runner_flag (
constant values : boolean_array_t)
return boolean is
begin
for i in values'range loop
if values(i) = true then
return true;
end if;
end loop;

return false;
end;

end package body run_types_pkg;
21 changes: 16 additions & 5 deletions vunit/vhdl/run/test/run_tests.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,9 @@ use vunit_lib.run_pkg.all;
use vunit_lib.runner_pkg.all;
use vunit_lib.core_pkg;

library ieee;
use ieee.std_logic_1164.all;

entity run_tests is
generic (output_path : string);
end entity;
Expand Down Expand Up @@ -130,7 +133,7 @@ begin
wait until start_test_runner_watchdog;
test_runner_watchdog(runner, 10 ns);
test_runner_watchdog_completed <= true;
runner.exit_without_errors <= false;
runner(runner_exit_status_idx) <= runner_exit_with_errors;
end process watchdog;

test_runner : process
Expand All @@ -149,8 +152,12 @@ begin
procedure test_case_setup is
begin
runner_init(runner_state);
notify(runner);
runner.exit_without_errors <= false;
runner(runner_exit_status_idx) <= runner_exit_with_errors;
if runner(runner_event_idx) /= runner_event then
runner(runner_event_idx) <= runner_event;
wait until runner(runner_event_idx) = runner_event;
runner(runner_event_idx) <= idle_runner;
end if;
end;

constant c : checker_t := new_checker("checker_t", default_log_level => failure);
Expand Down Expand Up @@ -803,10 +810,14 @@ begin
banner("Should be possible to externally figure out if the test runner terminated without errors.");
test_case_setup;
test_runner_setup(runner, "enabled_test_cases : test a,, test b,, test c,, test d");
check_false(c, runner.exit_without_errors, "Expected exit flag to be false after runner setup");
wait for 0 ns;
check_equal(c, runner(runner_exit_status_idx), runner_exit_with_errors,
"Expected exit with error status after runner setup");
p_disable_simulation_exit(runner_state);
test_runner_cleanup(runner);
check(c, runner.exit_without_errors, "Expected exit flag to be true after runner cleanup");
wait for 0 ns;
check_equal(c, runner(runner_exit_status_idx), runner_exit_without_errors,
"Expected exit without error status after runner cleanup");
test_case_cleanup;

---------------------------------------------------------------------------
Expand Down

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