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CLI: allow for extra plib and map files #284

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mole99 opened this issue Jan 23, 2025 · 4 comments
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CLI: allow for extra plib and map files #284

mole99 opened this issue Jan 23, 2025 · 4 comments
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@mole99
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mole99 commented Jan 23, 2025

synth_fabulous has support for -extra-plib and -extra-map to be used for User defined BELs.

The CLI currently has no option to supply those arguments. I marked this as a bug as I think this is an unintentional limitation of the CLI.


Side remark: As a user I am not too happy about "FABulous doing everything for me". Synthesizing the user bitstream and running PnR works well enough in an extra Makefile or shell script. Once the FPGA has been designed and taped-out, I would rather not use FABulous just to create a bitstream for a user design.

@mole99 mole99 added the bug Something isn't working label Jan 23, 2025
@KelvinChung2000 KelvinChung2000 added enhancement New feature or request and removed bug Something isn't working labels Jan 23, 2025
@IAmMarcelJung
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synth_fabulous has support for -extra-plib and -extra-map to be used for User defined BELs.

The CLI currently has no option to supply those arguments. I marked this as a bug as I think this is an unintentional limitation of the CLI.

We should probably make all the the options of synth_fabulous accessible in the CLI in the future. @KelvinChung2000 once mentioned that it probably easy due to the migration to cmd2 in #273 IIRC.

Side remark: As a user I am not too happy about "FABulous doing everything for me". Synthesizing the user bitstream and running PnR works well enough in an extra Makefile or shell script. Once the FPGA has been designed and taped-out, I would rather not use FABulous just to create a bitstream for a user design.

I think this depends on what the philosophy behind FABulous should be. Do we want it to be just a Fabric Generator, or more a general CAD toolchain with more features and external programs already included?
IMHO there is a charm in having the whole flow (or rather both flows) in one tool, so that you can both create a fabric and later also generate a bitstream for it. Especially for users that are not too familiar with all the CAD tools. And even if all of this is supported, its also perfectly fine to do it another way, if that fits your need better :)

If you want to discuss more about this we should probably move that part of the converstation to a discussion (sorry I'm a bit of a organisation maniac...).

@KelvinChung2000
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We have the CLI first, then have the synth command. So, the synth command does not support those options.

@mole99
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mole99 commented Jan 23, 2025

@IAmMarcelJung

As I was discussing with @EverythingElseWasAlreadyTaken on Tuesday, I'd really prefer if FABulous could be used as a tool instead of driving the flow. When designing an ASIC, generating the fabric and therefore FABulous is just one part of it. And I feel that trying to automate too much will lead to restrictions/limitations in other areas. I already feel this a little when using FABulous for my master's thesis.

Of course being able to use both options is fine if one does not restrict the other too much.

Taking a deeper look into OpenLane 2 and it's configurability shows that it takes a lot to make a flow both easy to use but configurable enough that it does not impose any restrictions on the user.

But like you said, that should probably be its own discussion by itself ;)

@EverythingElseWasAlreadyTaken
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EverythingElseWasAlreadyTaken commented Jan 23, 2025

synth_fabulous has support for -extra-plib and -extra-map to be used for User defined BELs.

The CLI currently has no option to supply those arguments. I marked this as a bug as I think this is an unintentional limitation of the CLI.

I'm currently working on supporting custom primitives and generating custom tiles out of the box. This includes also the integration in the FABulous synthesis/bitstream flow. This could partly solve your issue, but it will be mostly suitable for simpler designs.

Side remark: As a user I am not too happy about "FABulous doing everything for me". Synthesizing the user bitstream and running PnR works well enough in an extra Makefile or shell script. Once the FPGA has been designed and taped-out, I would rather not use FABulous just to create a bitstream for a user design.

The automated end-to-end flow, including the FABulous bitstream generation, is mostly designed for the general, but simple use case. For example, if you want to design a simple fabric, with only default tiles, you can do it in no time, without even thinking about how to do all the stuff.

But you don't have to use it that way. If you are doing more sophisticated design, then of course you should write your own flow for your user design. This is also one point, why bit_gen is not directly integrated in FABulous flow and build as a separate program. (But bit_gen also needs a rework at some point. 😄 )

We should maybe add some more documentation for the more sophisticated approach.

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