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Insights: FPGA-Research/FABulous
Overview
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- 6 Merged pull requests
- 0 Open pull requests
- 15 Closed issues
- 1 New issue
There hasn’t been any commit activity on FPGA-Research/FABulous in the last week.
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6 Pull requests merged by 5 people
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fabric_generator: Fix broken VHDL fabric generation
#309 merged
Jan 30, 2025 -
Add the new synthesis options
#291 merged
Jan 30, 2025 -
Improve FrameData and FrameStrobe handling
#306 merged
Jan 30, 2025 -
Update publications.bib
#247 merged
Jan 28, 2025 -
Fix run_simulation output
#307 merged
Jan 27, 2025 -
Add support for SystemVerilog in BELs
#304 merged
Jan 27, 2025
15 Issues closed by 2 people
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CLI: allow for extra plib and map files
#284 closed
Jan 30, 2025 -
non-matching result from run_simulation
#305 closed
Jan 28, 2025 -
Switch-Matrix contains commented-out ports
#201 closed
Jan 27, 2025 -
Waveform
#213 closed
Jan 27, 2025 -
Xs in Demo Project Simulation
#246 closed
Jan 27, 2025 -
Mux input ordering
#165 closed
Jan 27, 2025 -
Code Formatter
#158 closed
Jan 27, 2025 -
Separate Fabric and Tile description
#149 closed
Jan 27, 2025 -
synthesis error
#145 closed
Jan 27, 2025 -
Top Wrapper (eFPGA_top.v) Not Generated
#133 closed
Jan 27, 2025 -
nextpnr error
#118 closed
Jan 27, 2025 -
Demo W_IO problem/questions
#112 closed
Jan 27, 2025 -
"enum" parameter bitstream mapping
#52 closed
Jan 27, 2025 -
Improve VPR output instantiation
#41 closed
Jan 27, 2025
1 Issue opened by 1 person
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Replace VHDL bel parser with GHDL-Yosys plugin
#310 opened
Jan 30, 2025
3 Unresolved conversations
Sometimes conversations happen on old items that aren’t yet closed. Here is a list of all the Issues and Pull Requests with unresolved conversations.
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FABulous cleanup
#290 commented on
Jan 31, 2025 • 21 new comments -
CLI: `run_simulation fst` does not create FST file
#303 commented on
Jan 27, 2025 • 0 new comments -
Shell is entered instead of throwing an error when the script file is an existing directory
#302 commented on
Jan 27, 2025 • 0 new comments