An on-chip network router in Chisel.

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni

HotSpot v7.0 is an accurate and fast thermal model suitable for use in architectural studies.

Cost Model

Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)

NoC routers, simulators, and design tools for heterogeneous 3D SoCs

Ratatoskr NoC Simulator

BookSim 2.0

Network on Chip Simulator

FuseSoC standard core library

开放验证平台NutShell Cache验证案例

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-sp…

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

USB 2.0 Device IP Core

A full-speed device-side USB peripheral core written in Verilog.

Package manager and build abstraction tool for FPGA/ASIC development

DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator

The Unified TileLink Memory Subsystem Tester for XiangShan

Wavious High Speed Die-to-die

A Chisel RTL generator for network-on-chip interconnects

Advanced Interface Bus (AIB) die-to-die hardware open source

Handy Scripts For Doing Things

SystemC Reference Implementation

Xiaomi Home Integration for Home Assistant

Python tool for converting files and office documents to Markdown.

This will be a step by step guide for building ucb-bar/chipyard on Ubuntu