microprocessor202_matrix instruction

five-stage-pipeline riscv processor

Verilog implementation of Softmax function

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You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size of the systolic array can be changed, now it is 16X16.

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

Mirror kept for legacy. Moved to https://github.com/llvm/llvm-project

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A repository for recording the codes of machine learning algorithms